Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying relevant layout dependent issues in current recent CMOS technologies. It’s great to get fresh aspects from young engineers regarding an important topic in our industry.
Besides the known benefits of advanced CMOS technology nodes, which are moving towards the ultra-small nanometer range, the layout work for mixed-signal circuits is becoming more and more challenging. Several challenges, which were quite tamed in earlier technology nodes, are coming up as a bottleneck for design performance and robustness in current nodes. For new engineers who are working with such advanced nodes, these challenges are unknown to them because most of the undergraduate and graduate level classes do not cover layout challenges. Furthermore, ignoring such effects directly leads to performance differences between expected versus observed results. Early knowledge of these layout effects is required prior to design and layout in order to lessen future unpleasant surprises. This article covers generic but important aspects of layout that are needed to be taken care for the sake of performance and design robustness. This includes process selection, layout dependent, simulation’s out-of-scope, and invisible effects.
Process Selection Effect
The foremost point for engineers is to know the type of processes. The most common processes are bulk CMOS and silicon-on-insulator (SOI); each has their own pros and cons. Bulk CMOS process can be of highly or lightly doped type depending upon designers’ needs. A highly doped substrate has low risk of latch-up compared to a lightly doped substrate. In terms of substrate noise coupling, the lightly doped substrate offers better noise isolation between circuits due to small substrate coupling1.
The SOI process offers significant reduction in cross-talk between analog and digital circuits on the same die i.e., ease for integration2. It provides high performance passive elements for high frequency. It also provides lower junction capacitances, which reduce overall power consumption3. Due to aforementioned properties, it dominates the area of low power mobile applications. As SOI has no wells into the substrate; therefore, no latch-up issue occurs. Due to floating body, SOI designs exhibit threshold voltage variations, also known as history effect. It also suffers from self-heating, which can degrade analog circuit performance. Hence, knowing the process to be used is an important step for deciding which type of challenges will lie ahead during layout.
Layout Dependent Effects (LDEs)
One of the important aspects, which started to have great impact on circuit performance in newer technology nodes, are layout dependent effects (LDEs)4,5. LDEs are among the main reasons for having performance difference between schematic and extracted level simulations. These effects include well proximity effect (WPE), length of diffusion (LOD), oxide-to-oxide spacing effect (OSE), poly spacing effect (PSE), etc. as shown in Figure 1. The WPE is due to substrate doping non-uniformity; it comes from edge effects during ion-implantation. This has a direct impact on transistor’s threshold voltage, which affects matching and performance. Another important effect is LOD, which comes from silicon stress caused by shallow trench isolation (STI). It has impact on transistor’s mobility; however, it affects NMOS and PMOS differently.
Layout dependent effects
A compressive stress increases (decreases) PMOS (NMOS) mobility. The impact of this effect decreases exponentially with the distance from the STI. Another effect is OSE, which reflects the amount of STI stress in transistors with different active area spacing. The PSE, which started showing significant effect in newer technology nodes, is due to the poly-to-poly distance and has an effect on transistor’s electrical parameters.
Depending upon the setup of the process design kit (PDK) and circuit simulator, predicting some of these effects in schematic can be handled through simulation parameters. For circuits, usage of dummy cells and symmetricity in the design with respect to edge are some of the ways to handle such effects.