**Question:**

Is placing a 100Ω resistor in front of a MOSFET gate required for stability?

**Answer:**

Ask any experienced electrical engineer—for example, Gureux, the professor in our story—about what to put in front of a MOSFET gate and you will probably hear “a resistor, approximately 100 Ω.” Despite this certainty, one still wonders why and questions the utility and the resistance value. Because of that curiosity, we will examine these questions in the following example. Neubean, a young applications engineer, looks to test if it is actually necessary to place a 100Ω resistor in front of a MOSFET gate for stabilization. Gureux, an applications engineer with 30 years of experience, monitors his experiments and gives his expert opinion along the way.

**Introducing the HS Current Sense**

**Figure 1**

The circuit in Figure 1 shows a typical example of high-side current sense. Negative feedback tries to force the voltage V_{SENSE} upon gain resistor R_{GAIN}. The current through R_{GAIN} flows through P-channel MOSFET (PMOS) to resistor R_{OUT}, which develops a ground referenced output voltage. The overall gain is

Optional capacitance C_{OUT} across the resistor R_{OUT} serves to filter the output voltage. Even if the drain current of the PMOS quickly follows the sensed current, the output voltage will exhibit a single-pole exponential trajectory.

The resistor R_{GATE} in the schematic separates the amplifier from the PMOS gate. What is the value? “100Ω, of course!” the experienced fellow Gureux might say.

**Trying Out Lots of Ω**

We find our friend Neubean, a student of Gureux’s, pondering this gate resistor. Neubean thinks that with enough capacitance from the gate to the source, or with enough gate resistance, he should be able to cause stability problems. Once it is clear that R_{GATE} and C_{GATE} interact detrimentally, then it will be possible to debunk the myth that 100 Ω, or in fact any gate resistance, is automatically appropriate.

**Figure 2**

** High-side current sense simulation.**

Figure 2 shows an example of an LTspice simulation used to highlight the circuit behavior. Neubean runs simulations to show the stability problems that he believes will occur as R_{GATE} increases. After all, the pole from R_{GATE} and C_{GATE} ought to erode the phase margin associated with the open loop. Yet, to Neubean’s amazement, no value of R_{GATE} shows any sort of problems in the time domain response.

**Turns Out, the Circuit Is Not So Simple**

**Figure 3**

**Frequency response from the error voltage to the source voltage.**

In looking at the frequency response, Neubean realizes he needs to take care of identifying what the open loop response is. The forward path that forms the loop, when combining the unity negative feedback, starts from the difference and ends at the resulting negative input terminal. Neubean then simulates and plots V_{S}/( V_{P} – V_{S}), or V_{S}/ V_{E}. Figure 3 shows a plot’s frequency domain plot for this open-loop response. In the Bode plot of Figure 3, there is very little dc gain and no evidence of phase margin problems at the crossover. In fact, the plot overall looks very strange as the crossover frequency is less than 0.001 Hz.

**Figure 4**

**High-side sense circuit as a block diagram.**

The decomposition of the circuit into a control system appears in Figure 4. The LTC2063, like almost all voltage feedback op amps, starts with high dc gain and a single pole. The op amp gains the error signal and drives the PMOS gate through the R_{GATE} – C_{GATE} filter. The C_{GATE} and PMOS source connect together to the –IN input of the op amp. R_{GAIN} connects from that node to the low impedance source. Even in Figure 4, it might appear that the R_{GATE} – C_{GATE} filter should cause stability problems, particularly if R_{GATE} is much larger than R_{GAIN}. After all, the C_{GATE} voltage, which directly affects the R_{GATE} current in the system, lags op amp output changes.

Neubean offers one explanation to why perhaps R_{GATE} and C_{GATE} do not cause instability: “Well, the gate source is a fixed voltage, so then the R_{GATE} – C_{GATE} circuit is irrelevant. All you need to do is adjust the gate and the source follows. It’s a source follower.”

His more experienced colleague Gureux says, “Actually, no. This is only valid when the PMOS operates normally as a gain block in the circuit.”

Thus prompted, Neubean thinks about the math—what if we could directly model the response of the source of the PMOS to the gate of the PMOS? In other words, what is V(V_{S})/V(V_{G})? Neubean runs to the white board and writes the following equations.

with

op amp gain A, and op amp pole ωA.

Neubean immediately identifies the important term gm. What is gm? For a MOSFET,

Looking at the circuit back in Figure 1, a light bulb goes off in the Neubean’s head. With zero current through R_{SENSE}, the current through the PMOS ought to be zero. With zero current, gm is zero, because the PMOS is effectively off, not being used, unbiased, and has no gain. When gm = 0, V_{S}/ V_{E} is 0 at 0 Hz and V_{S}/ V_{G} is 0 at 0 Hz, so there is no gain at all and the plots in Figure 3 may be valid after all.