Analog IC layout relies on the schematic as a starting point, conveying not only information about the connectivity of the devices in the circuit, but also the design intent. Traditional approaches have been to use the DRC (design rule check), ERC (electrical rule check) and LVS (layout versus schematic) checking tools to iterate manual layout until the desired layout topology is correct according to the design rules and required connectivity. Often notes are used in the schematic to indicate constraints or to guide the layout engineer, or the use of a constraint-driven methodology for layout tools that can automatically produce layout according to these constraints. Despite these advances, layout engineers still make use of experience in order to generate correct physical design.
While DRCs are often easy to interpret and correct, ERC and connectivity checks (LVS) can be more difficult. Interpreting an LVS error report remains challenging, especially with power/ground shorts that can occur over levels of a design hierarchy. And in general, such checks are only useful when a design is nearing layout completion, thus giving potentially long turnaround times before the layout is adequate for extraction and post-layout simulation.
Furthermore, todayís more complex processes can cause new and more complex errors to occur that can take time to debug. A typical example is with deep Nwell processes, which provide an additional level of isolation to traditional CMOS processes to give better noise performance.
In a deep Nwell process, Nmos devices have a buried N well to provide isolation between their bulk node and the P substrate. This allows these devices to have different bulk potentials; however, to achieve this the devices need an isolating Nwell guard ring to prevent bulk node shorts, as shown in Figure 1 and 2.
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Nmos devices with bulk nodes that require isolation from the substrate
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Nmos devices have been isolated in concentric guard rings over deep Nwell.
Similar problems can occur with 3 terminal resistors or capacitors, whose 3rd terminal is a well or substrate connection, and may need isolation from other devices. Unfortunately, this additional level of isolation required can introduce errors, and isolation rings and well connections can be missed, or only found when the design is nearing completion and all levels of hierarchy are present.
What is required is automatic checking of designs as they are constructed, so that the necessary guard rings and isolation can be introduced as needed. For example:
- Deep Nwell layers should not overlap other deep Nwell or Nwell layers on a different net.
- Nmos devices with bulk pins on different nets need isolating by deep Nwell and Nwell guard rings
- Deep Nwell needs to be tied off to a suitable net to ensure the deep Nwell / P well junction remains forward biased at all times.
- Floating wells (e.g. P wells in a N well ring over deep N well) need a P+ guard ring or tap.
By using automatic layout generation, these checks will not only always be made but also always adhered to, and so the likelihood of connectivity errors can be greatly reduced.
In summary, ever shortening time to market and increased design and process complexity, puts more pressure on achieving correct layout in a timely manner. Old methods of manual circuit design, layout and verification need to be updated to prevent long iterative debug cycles to fix errors. Correct-by-construction layout is the goal, giving LVS and ERC correct designs without expensive rework. Pulsicís Animate automatic layout generation is an example of modern approaches to correct-by construction layout.
- Navigating the mixed-signal maze, John Pennock, Chip Design Magazine, April/May 2004.
- Using Deep Nwells in Analog Design, Keith Sabine, Planet Analog, 7th May 2015.