The level of automation applied to analog design has never approached the level enjoyed by digital designers. For years designers have iterated through schematic entry, physical layout, parasitic extraction, and simulation, as shown in Figure 1. As the layout has traditionally been done manually with "polygon pushing" tools, generating the layout can take days for a typically sized block.
Traditional manual analog layout flow
The schematic of such a traditional flow as shown in Figure 1 usually contains just text notes for constraints. These are then handed over to the layout engineer. The devices (transistors, resistors, etc.) are then created in layout from the schematic, followed by manual placement and routing (according to constraint notes) -- both of which need to be repeated through verification until clean.
Once a clean layout has been achieved, the parasitics can then be extracted for re-simulation, and the whole cycle then needs to be repeated until the simulation results show the required performance has been met. With the considerations of time-to-market being ever more important, and new processes requiring higher-quality parasitic information as early as possible, this whole flow is too repetitive and far too slow.
Why layout automation has not been successful so far
Circuit designers need a way of exploring different floor plans quickly, and getting feedback for simulation in a short timeframe. However, all automation attempts to date have failed to generate layouts of sufficient quality (DRC/LVS correct), layouts that are too far removed from what an experienced analog designer would do by hand -- so they do not facilitate this convergence. There are several reasons these have failed.
Typically, EDA vendors have tried to apply digital placement and routing technologies or techniques to the analog layout problem. This will never yield the results an analog designer is looking for in terms of quality of results, or in terms of considering the complex constraint requirements for analog. Constraint setup itself is a huge problem, so much so that it is usually quicker to do the layout manually than enter all the constraints. Finally, the tool flow, setup, training, and use model has been too complex for many analog designers.
A new automated approach
What is needed is a new flow that gives good floor plan estimates early in the design cycle, together with good parasitic estimates so that excessive overdesign can be avoided. This will be a necessity for the latest process geometries. Multiple floor plans should be generated so the designer can explore the optimal layout for the design and pick the best one for his needs.
Placement and routing cannot be done separately. They need to at least be co-dependent to ensure that the design can be routed 100 percent with optimal area, while meeting the required constraints to ensure a good-quality layout. This is vital -- a "trial" or "prototype" layout will not suffice.
Constraint generation should be as automatic as possible by recognizing common circuit topologies. However, the user should be free to choose to modify these constraints to enable him or her to home in on the desired floor plan in a simple user-friendly way.
And above all, the automated approach should require the minimum setup and have a simple, easy-to-use GUI so users can be productive with minimal training.
Figure 2 shows such an automated analog layout flow.
Automated analog layout flow
In this flow, you open a schematic straight from OA (the Open Access database) into an automated layout editor, which would then proceed to create all the necessary devices and concurrently place and route them to generate DRC and LVS clean layouts (in several variants). Extraction of parasitics can then be done for simulation. If performance is not met, then the designer can make schematic or constraint changes until it is -- but the whole process needs to be simple and fast.
Although the process described should be as automatic as possible, designers will always need the ability to make minor changes. So having some new-generation editing tools will also help to reduce the design time when finalizing designs -- rather than reverting to traditional polygon editing, which has every chance of breaking DRC/LVS or constraints.
Benefits of the new approach
As the new flow will be required to be simple to use, it can be used by circuit designers early to get faster, more accurate simulation results and thus reduce iterations. It can be used by floor planners to get accurate estimations of block sizes and aspect ratios to speed up top-level design; and it can be used by layout engineers to design more optimal layouts with fewer retries and fewer iterations traditionally caused by DRC/LVS violations.
Let us know your experience using layout tools. What problems have you had, and how have you overcome these problems?