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Keith Sabine

Is It Time for Custom Design Tools to Catch Up With Digital?

Keith Sabine
Netcrawl
Netcrawl
4/22/2014 8:29:12 PM
User Rank
Master
Re: Excellent Article I will use it
Excellent post! thanks for that @Keith, layout is still key in every engineering works and it can be effectively build using EDA software. The benefits of using EDA tools is that can automate everything like PCB timing closure, saving us both on time and effort and speeding up the processing. 

 

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etnapowers
etnapowers
4/22/2014 4:42:34 AM
User Rank
Master
Re: Excellent Article I will use it
Yes, you're right, layout is really important, for example to prevent cross talking of RF modules by mean of a proper insulation. The cross talking is difficult to simulate and to prevent and it might generate failures many times, so it's important to realize a smart designing of the layout.

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etnapowers
etnapowers
4/22/2014 3:44:16 AM
User Rank
Master
Re: Excellent Article I will use it
The layout design is very critical, many effects due to packaging for example are difficult to be simulated but they can create concerns many times on the applicative circuitry.

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DaeJ
DaeJ
4/21/2014 3:31:20 PM
User Rank
Master
Re: Excellent Article I will use it
Layout would be designed to keep the package parasitic current to a minimum. Antenna mount and design could be one of critical portions in the PCB.

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Hillol
Hillol
4/21/2014 12:32:37 PM
User Rank
Newbie
Excellent Article I will use it
Like to discuss more on this. Layout is very critical for Analog and RF.

 

Hillol.Sarkar@ago-inc.com

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More Blogs from Keith Sabine
Although digital design productivity has improved massively since the introduction of synthesis, advanced place and route and timing-driven design, analog design still relies on circuit simulation, manual layout and verification.
On a conventional CMOS process, NMOS devices are formed in a P well or substrate connected to ground (or the most negative supply in the circuit). PMOS devices are formed in an N well connected to the most positive supply
Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions they were connected to.
Analog designers have always had to worry about physical layout to get good matching of devices.
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