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Keith Sabine

Using Deep N Wells in Analog Design

Keith Sabine
Keith Sabine
Keith Sabine
5/8/2015 4:32:13 AM
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Re: DNW vs PDSOI for analog
There has been some research into noise performance of SOI compared to deep N well process technology (I can't publish the link, this site won't allow URL posting) but if you google for "Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC" you should find it.

The problem is that with SOI, the coupling capacitance from the devices is relatively high, as shown in the paper, and the noise performance is worse than deep N well technology. And then you have the cost overhead of SOI wafers over conventional silicon.

Silicon on sapphire would get round the substrate coupling, but not the cost issue, and has long been used for rad-hard environments, where cost is not a real problem.

5/7/2015 3:50:17 PM
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DNW vs PDSOI for analog
Curious about your take on the relative merits of a deep Nwell

and a thick film SOI (partially depleted) for analog performance,

noise, layout density and cost.


My observation is that density may be a wash (DNW oversize

of Pwell often being quite large, but dtrench also needing a lot

of room to minimize strain effects), SOI having an absolute lack

of substrate leakage and an ability to make each device body

ohmically tied & independent, but DNW having only two added

implants vs the greater challenges of high aspect ratio trenching

(and potentially some poly-routing contraints, like no poly over



Have you an opinion, or direct comparo data, on the performance

when it comes particularly to noise limited analog performance,

between these two approaches?

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