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Keith Sabine

Constraint-driven Analog Placement and Routing

Keith Sabine
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There has been vast progress over the last 30 years or so in digital layout automation, which has made it possible to develop complex digital ICs relatively quickly. However, for analog layout, techniques are still much the same as they were years ago.
On a conventional CMOS process, NMOS devices are formed in a P well or substrate connected to ground (or the most negative supply in the circuit). PMOS devices are formed in an N well connected to the most positive supply
Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions they were connected to.
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