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Sureena Gupta

Powering Your FPGA? Reduce Footprint Size

Sureena Gupta
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fasmicro
fasmicro
11/9/2013 8:01:10 PM
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Re: Cell Size
>> This mode is controlled by the dedicated pin. Then, this mode latches all logic arrays. 

That takes care of your dynamic power but has not solved the problem of your static power dissipation. Nevertheless, great idea but will be challenging for a more complex circuit

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yalanand
yalanand
10/27/2013 7:10:28 AM
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Re : Powering Your FPGA? Reduce Footprint Size
When operating a solution that contains an FPGA, you require a number of output voltage rails with dissimilar loads.  Quite a few of those rails need to control up and down successively according to system necessities and FPGA needs. 

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B_Albing
B_Albing
10/23/2013 9:58:46 PM
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Editor
Re: Cell Size
@DaeJ - OK - you're looking at super-low power applications. Understood.

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DaeJ
DaeJ
10/23/2013 7:57:00 PM
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Master
Re: Cell Size
My intention is to get zero amps instead of a few hundred micro amps for parasitic current. To achieve this goal, I think that each D flip-flop register with other register would be completed sleep mode by using bit controller of each cell.

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B_Albing
B_Albing
10/22/2013 4:08:06 PM
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Editor
Re: Cell Size
@DaeJ - Not completely sure if you meant that you would use a shift register to sequencially enable multiple power supplies. But if you did, note that you could do the sequencing with a shift register, but it would not give you as much flexibility as a device designed specifically to do power supply sequencing like the UCD90120A.

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samicksha
samicksha
10/21/2013 7:21:08 AM
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Artist
Re: Cell Size
If we account on FPGA power consumption can only accounted on function it is performing and the frequency it is operating at.

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DaeJ
DaeJ
10/18/2013 8:21:30 PM
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Master
Re: Cell Size
I would look at the power down mode that FPGA consume near-zero power. This mode is controlled by the dedicated pin. Then, this mode latches all logic arrays. The present gate would be a frozen state.

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fasmicro
fasmicro
10/18/2013 3:50:03 PM
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Master
Re: Cell Size
>>  So, I think that Power consumption of chip would be depending on the total number of cell size inside chip.

The key factors that determine power consumption is capacitance, voltage and the frequency (0.5CfV^2). So, if you increase the cell size while keeping the total capacitance low (the parasitics), you can still be fine with power. The frequency does not scale with chip size, it is simply the clocking speed.

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Pho99
Pho99
10/18/2013 10:00:55 AM
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Newbie
Source of good info on the Zynq FPGA/SOC
www.programmableplanet.com has information on the Zynq that will move to Programmable Logic Design Line on EETImes in the comming days.

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samicksha
samicksha
10/18/2013 3:16:04 AM
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Artist
Re: Cell Size
I read about Zynq-7000 that fused features of an ARM high-end microcontroller with FPGA fabric to make FPGA easier for embedded designers, any more info on same.

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