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Maithil Pachchigar

ADCs for High Dynamic Range: Successive-Approximation or Sigma-Delta?

Maithil Pachchigar
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DaeJ
DaeJ
9/14/2014 7:42:57 PM
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Master
ADC for analog signal above 1 GHz
Oversampling might be not a solution for this case. Solution might need multiple signal conversion stages such as filtering to get the right frequency signal. Incorrect ADC process might produce unwanted interleaving artifacts, causing misinterprets the original input signal. I am wondering if there is a method to get the ADC, related to post processing.

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samicksha
samicksha
9/11/2014 2:23:04 PM
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Re: Oversampling with SAR
I understand your but i just tried taking reference, although i accept that oversampling is process of sampling the input signals at much higher rate.

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DaeJ
DaeJ
9/1/2014 11:36:11 AM
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Master
Re: Oversampling with SAR
It could be depending on application between data converter and other device used in the application. ADC latency could be measured in the clock cycle. Each latency could be considered from analog front end to digital output with propagation delay (Tpd) measuring the delay on clock input and on clock output and data. Also, with overall system latency review, ADC resolution could be selected by designer.

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Victor Lorenzo
Victor Lorenzo
8/30/2014 11:23:33 AM
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Re: Oversampling with SAR
The ADC architecture and its digital interface determine the convertion time, or better said, the time it takes for having the sample stored in the CPU memory and ready for processing.

SAR ADCs can exhibit a longer "effective" convertion time when interfaced using SPI or multiplexed data bus than with a full word sized parallel data bus (considering the same conversion clock speed).

 

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vasanjk
vasanjk
8/30/2014 1:52:38 AM
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Re: Oversampling with SAR
@tzubair,

 

Nowadays so much of information is available that helps in deciding on peripherals early in the design life cycle. Normal practice would be to freeze ADC specs at the design stage itself. The decision between selecting a 12bit ADC and a 10 bit software oversampled ADC is taken probably at the start itself.

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vasanjk
vasanjk
8/30/2014 1:49:01 AM
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Master
Re: Oversampling with SAR
Samicksha

 

A single conversion time may not be important. During oversampling, several samples are taken and data manipulated. This "no of samplesX conversion time" could impact the overall data thoroughput.

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samicksha
samicksha
8/29/2014 3:53:56 PM
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Artist
Re: Oversampling with SAR
I guess the key here is conversion time, conversion time is very short. When we consider10-bit ADC with a clock frequency of 1 MHz, the conversion time will be 10 microseconds.

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tzubair
tzubair
8/29/2014 2:21:27 PM
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Master
Re: Oversampling with SAR
@Maithil: I think it also depends on the nature of application. For an R&D experiment in the lab, performance would be the key priority because that can't be compromised on. For a production environment, cost would be more important because the quantity would need to be procured in a bulk quantity.

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Maithil Pachchigar
Maithil Pachchigar
8/29/2014 10:24:29 AM
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Newbie
Re: Oversampling with SAR
You would need to consider tradeoffs between 10-bit and 12-bit ADCs based on performance, space, power, and cost requirements.

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vasanjk
vasanjk
8/29/2014 7:40:11 AM
User Rank
Master
Re: Oversampling with SAR
MP

 

I have read this app note and a similar one published by SilabS and I implemented it in a Renesas MCU design with good results.

 

My question is between a 12 bit ADC and an oversampled 10 bit ADC, how could one decide based on the pros of both?

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Page 1 / 2   >   >>
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For data acquisition systems, sometimes a successive approximation ADC works best. Other times, a delta-sigma is the best choice. Consideration must also be given to the multiplexer. Let's see what works best and why.
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