[Editor's note: Another ADI look into the world of electronics mystery from the series "Rarely Asked Questions: Strange but True Stories From the Call Logs of Analog Devices" guest authored by Maithil Pachchigar, a Planet Analog blogger.]
Q: I need 100-dB dynamic range for a medical imaging application. Can you help me choose between successive-approximation and sigma-delta ADC architectures?
A: High-performance data-acquisition signal chains used in industrial, instrumentation, and medical equipment require wide dynamic range and high accuracy. The dynamic range of an ADC can be increased by adding a programmable-gain amplifier or operating multiple ADCs in parallel, using digital post-processing to average the result, but these methods can be impractical due to power, space, and cost constraints. Oversampling allows an ADC to achieve high dynamic range at low cost, while also addressing tough space, thermal, and power design challenges.
Oversampling is performed by sampling the input signal at much higher rate than the Nyquist rate (twice the signal bandwidth) to increase the signal-to-noise ratio (SNR) and effective number of bits (ENOB). When the ADC is oversampled, the quantization noise is spread such that most of it occurs outside the bandwidth of interest, resulting in increased overall dynamic range at low frequencies. The noise outside the bandwidth of interest can be eliminated using digital post processing as shown in Figure 1. The oversampling ratio (OSR) is the sampling rate divided by the Nyquist rate. The improvement in dynamic range (ΔDR) due to oversampling is Δ DR = log2 (OSR) × 3 dB. For example, oversampling the ADC by a factor of four provides a 6-dB increase in dynamic range, or one additional bit of resolution.
Oversampling of Nyquist ADC
Oversampling is inherently implemented in most sigma-delta (Σ- Δ) ADCs with integrated digital filters, where the modulator clock rate is typically 32 to 256 times the signal bandwidth, but Σ- Δ ADCs are limited for applications that require fast switching between input channels. The SAR architecture has no latency or pipeline delays, enabling high-speed control loops and fast switching between input channels, and its high throughput rate allows oversampling.
Although both ADC topologies can accurately measure low-frequency signals, the power consumption of a SAR ADC scales with throughput rate, reducing power consumption by at least 50% as compared to Σ- Δ ADCs, which typically consume a fixed amount of power. ADI's AD7960 5-MSPS, 18-bit SAR ADC provides an example of high throughput rate with linear power scaling.
The low-pass filter placed in front of a SAR ADC minimizes aliasing and reduces noise by limiting bandwidth. The high oversampling ratio and digital filter of Σ- Δ ADCs minimize the anti-aliasing requirements at their analog inputs, and oversampling reduces the overall noise. For added flexibility, custom digital filtering can also be performed on the FPGA.
The low noise floor and high linearity of high-performance SAR ADCs allow them to provide increased bandwidth, high accuracy, and discrete sampling in a small time window required for fast measurement and control applications. Their high throughput rate, low power, and small size helps designers meet space, thermal, power, and other key design challenges common to high-channel-density systems. SAR ADCs also offer the lowest noise floor relative to the full-scale input signal, resulting in a higher SNR and excellent linearity, but unlike Σ- Δ ADCs they cannot reject 1/f noise close to dc (50/60 Hz).
SAR and Σ- Δ ADCs each have their own pros and cons. The data-acquisition system designer must make tradeoffs based on performance, speed, space, power, and cost requirements.