In part 1 of this series, we looked at the problems one encounters when trying to make a very low on-resistance power switch. The next step in building the device is to add the interconnect from silicon to the IC pins. Clearly, we don't want all the current to flow through the relatively high resistance metal layers and encounter sheet resistances. We can do several things to reduce the contribution of the sheet resistance.
- Create many parallel paths: If a bond wire is attached to the end of a trace with resistance R, MOS devices at the end of the trace see a series resistance of R. Compare this to the bond wire attached to the middle of the trace. Now there are two paths of R/2, resulting in net R/4 from bond wire to end.
- Make the currents flow mostly vertically: This requires to current to spread out in the top layers (one layer for source and one for drain) and then use lots and lots of vias from the top to the silicon. It turns out that many (stacked) vias have a lower resistance than a piece of metal trace. A typical via can have a resistance of 10Ω. Stacking five vias in a six-metal-layer process results in 50Ω per via stack. In a square millimeter, we could probably put a million vias -- 500,000 each for source and drain. Let's assume 200,000 vias for source and drain each (we can't place them everywhere). Then the total resulting resistance is half a milliohm -- sufficiently small for our purposes.
- Alternate drain and source metal: This brings drain and source close together everywhere, promotes vertical current flow, and creates parallel paths. From the top metal layer, we need to go to the outside world. Bond wires are the traditional choice, but one bond wire can easily have more than 100mΩ of resistance. We would need many (thick) bond wires to bring the contribution down a milliohm. For the 10mΩ switch, a better choice would be solder bumps or (even better) copper pillars. Now we're talking about wafer-level chip scale packages (WLCSPs), which are superior in size, lead resistance, inductance, and capacitance. The thermal performance is not as good as a QFN with exposed pad, but adding a heat spreader or heat sink can make the WLCSP thermally superior with Rthj-a below 20 K/W.
Of course, all these good properties come at a certain cost. Again looking at the 10mΩ resistance budget, we find that we probably need about 2mm2 of area for the NMOS, thick top metal, and bumps rather than bond wires. The NMOS Rds_on may be less than 50 percent of the total on-resistance.
To predict the resistance of a certain layout, we can make a resistor model of the entire metal stack and the MOS devices. One way I have done this is to cut the structure in squares and create a resistor model of one such square -- a unit. Usually a repeating pattern can be found. There may be different types of units in one switch structure. Repeat and connect the units in a schematic in the same way they appear in the layout. Once you have a schematic, the simulator will calculate the net on-resistance. You can also see the distribution of voltages and currents in the design. The variation in currents in the device should be as small as possible. There is some control over this by playing with the number of vias in certain locations.
A current ratio Imax/Imin < 2 has resulted in a well-performing power switch with a current limiter. The model will also be of help in determining the effects of the placement of the bumps or bond wires or where to place the senseFETs (to be discussed another time). A modular model like this allows for easy experimentation with the construction and the number of metal layers. You may find that six metal layers result in a slightly lower total resistance than four layers. Depending on the device construction, more layers can give more paths for the current to flow, thereby lowering the resistance beyond the increase due to a higher via stack.
Now that we have an idea how to design the switch, we can start looking at the electrical features these switches offer. That will be a subject for a future blog.