So I have been thinking about the design environment for analog designers and the challenges that plague mixed signal design engineers in the new technology space as we design on process nodes that have significant layout dependent effects (LDE) as well as strong correlation among devices. The challenge from a design perspective is complicated. Typically in the past the designer relied on corner simulations to provide feedback into how a circuit will behave in silicon that meets required design for manufacturability goals set by the company. So the question is what happens when the designer in these new technologies cannot rely on corner models but must run extracted simulations even at the block level because of all the LDE effects and correlations and interdependencies amongst devices?
I co-authored a paper with some colleagues that addresses the concern about corner models that hits on part of the problem I will discuss in this article. The article is “Corner Models: Inaccurate at Best, and it Only Gets Worst…” (Proc. IEEE CICC, 2013). Here is a brief statement from the conclusions drawn in the article that highlight some of the issues: corner models “cannot accurately bracket +/- 3σ variation in every performance measure for every circuit; “appropriate” corner models are not just circuit dependent, they also vary with the device sizes and biases used within a single circuit, and can be different for different measures of circuit performance for the same circuit.” I recommend the readers of this article spend some time and read this paper.
This paper mentioned highlights some of the reasons why corner models will not work for complex mixed signal design but why. Look at this image from a paper I presented at a modeling conference (Figure #1).
Figure #1: Effects on global and local parameters as the technology shrinks.
As shown in the image, as we shrink the technology, the global variations and local mismatch merge and it is no longer valid to just run corners. Furthermore, if we look at the electrical performance of transistors and devices as the technology shrinks we start seeing more interdependencies through LDE including pattern densities and device performance.
Simply put if we look at the variance of two random variables in these smaller technologies, there exists correlation amongst the parameters. Shown in equation #1 is the variance of two generic parameters X &Y. If the expected value is computed for the variance of these two parameters that are correlated, the result (Equation #1) shows that a covariance exists that cannot be ignored for high performance analog.
Therefore, with all of the mentioned effects that can change performance designers of complex high performance analog circuits are going to have to run statistical simulations to have confidence that the circuit is behaving as we desire to meet performance targets. But how when there are so many devices? This is the topic I would like to focus on next.
As stated, the smaller technologies have significant layout dependent effects that cause devices to behave differently from a simple schematic representation of a circuit. The full effect of the LDE parameters are usually only accessible through some type of extracted layout of the final circuit. This means that typically the extracted circuit is a flat netlist representation of the circuit represented in the schematic. So as already stated, because of the smaller geometries and the correlation that exists between devices, we need to run statistical simulations to understand the true performance of a circuit where there are strong interdependencies through layout and device parameter correlations.
So what does this mean for the designer that must run extracted statistical simulations? In the landscape of tools available to designers that run extracted simulations, there are limited options for selecting devices from extracted netlists for inclusion in a statistical simulation. This means that the idea of selecting devices for statistical simulations from the schematic is no longer a viable option. So what can be done? To address these issues many designers may just select the top level instantiation of the circuit in question by selecting /I*/I* etc. This allows the designer to not have to pour through the netlist to select the transistors desired to vary in a random manner.
Will this work? In some cases maybe but the number of devices and parameters that exist creates another problem that will be discussed shortly. What if the designer selects the particular devices that are desired to vary by pouring through the netlist? I would say that given the interdependencies as I stated earlier, selecting the correct devices to vary is problematic unless the designer knows the sensitivities in his or her circuit. Let’s investigate further.