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Ken Coffman

SOA, Watts Up, Transistor?: A Mystery of Self-Destructing MOSFETs

Ken Coffman,Bay Area, Senior, Principal Field Applications Engineer, Intersil
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JamesLankford
JamesLankford
11/18/2016 8:41:15 AM
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Way cool! Some substantial focuses extremely! I welcome you

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taylor123az
taylor123az
11/6/2016 7:02:21 AM
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Re: good post
I agree with you at this point

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Ken.Coffman
Ken.Coffman
10/25/2016 9:46:33 PM
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Re: psoriasis
That's nice of you to say, Monica. Jon and I really appreciate it.

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Thomas7
Thomas7
10/25/2016 3:07:33 PM
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Re: Yuwegedusitesnaszemedia
Great and informative post!

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Hooey0
Hooey0
10/24/2016 8:11:19 PM
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Re: Self Destructing MOSFET's
Ken - Thanks for the response. This is a great thread, with a ton of very useful information for desginers of circuitry requiring both linear and switch mode MOSFETs.

I had the opportunity to deal with this exact issue a few years ago when a subcontracted electronics board used the wrong type of MOSFET for a linear application. We burnt up quite a few devices in the process until we became aware of what the root cause of the failures was. The designer had never heard of the Spirito Effect before, but he sure did afterwards...

I have a PDF file from IR (P. Spirito worked there), but I don't see any way to attach it. It's IR application note AN-1155 for those who are interested.

Note that there's more information availaable on this subject, as I noted in my earlier post.

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Ken.Coffman
Ken.Coffman
10/24/2016 3:10:21 PM
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Re: Self Destructing MOSFET's
Yes, Hooey, you're right, we should have mentioned the Spirito Effect as a name for what we are describing. This is the thermal instability region where the VGS threshold has a negative temperature coefficient. At higher VGS, the thermal goefficient goes positive, which is helpful in helping FET cells to share current. For trench devices, operating with a low VGS is very dangerous and the SOA capability can be very much lower than what you expect. For trench FETs that don't show the Spirito bend on the right side of the SOA plot, be very suspicious of the SOA capability.

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David_Ashton_EC
David_Ashton_EC
10/22/2016 10:12:04 PM
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Re: Tiny schematic
Thanks Ken.  There's a lesson in interpreting Datasheet info in here!  I know most MOSFETS are used in pulse mode in SMPSs, but I've always been wary of the claimed dissipation ratings for the usual small TO-220 packages, even on good heatsinks.  Thanks again.

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Ken.Coffman
Ken.Coffman
10/22/2016 12:10:56 PM
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Re: Self Destructing MOSFET's
You make good points, Jerry. One thing that is interesting is what "test to fail" means. For Fairchild (and probably most everyone else, but I don't know), test to fail meant the die reached the high operating temperature (usually 150C or 175C). The silicon is not actually damaged at that temperature, so there is some margin at that limit. I was always more interested in the operating point where the die is actually being damaged, but it's time-consuming and tedious to collect that data for all the operating points in the SOA curve. 

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Ken.Coffman
Ken.Coffman
10/22/2016 12:02:58 PM
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Re: Tiny schematic
You're right, David. This is an active load circuit, so it's intended to draw a calibrated DC current. We're working on getting a higher resolution schematic. There are standard methods of testing SOA, but even when I was in the power FET busines (Fairchild), there were few that really understood how the data was collected and what it means. And worse, there was no guidance to extrapolating the test results to an actual circuit. SOA is generally tested with a cold plate fixed at 25C. How many designs ship with an infinite heat sink? When we did specific SOA testing for a customer, I was shocked at how wide the variance was--and that's with a captive fab, I can only imagine the situation is worse with an outsourced fab. Let the FET buyer beware.

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ethan77
ethan77
10/20/2016 4:52:50 PM
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Re: Self Destructing MOSFET's
Is that old transistor systems approach the stereo channels today?

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