Editor’s note: I am pleased to have Ken Coffman and his partner-in-crime in this excellent blog, Jon Dutra, Principal Electrical Engineer, Microsoft.
Being an engineer is often like being a detective. Clues are studied. Data is collected. Deductions are, uh, deduced. Pipes are smoked. No, wait, that’s Sherlock Holmes.
In this case we have a circuit that worked well at one operating point, but reliably self-destructed at another operating point. The active load circuits were the same. The transistor power dissipation was the same. The engineer pulls out his hair and cries out to the heavens: ‘What is going on?’
In this circuit, we have a pair of parallel power transistors in a constant current load, with each FET dissipating 18W. One design delivers 18A with VDS at 1V with great reliability. The modified circuit delivers 1.5A with VDS at 12V. It lets the smoke out. The power dissipation in the FETs is the same, so the failure rate should be the same, right? Not so fast, Doctor Watson.
Generally speaking, Safe Operating Area (SOA) is a poorly understood parameter. If you don’t believe us, ask your FET supplier to explain how the SOA test is performed and what the results mean in a typical design. Good luck with that.
From the FET datasheet (because we’re serious professionals, we won’t mention the vendor—wait, yes we will, it’s ST and the part number is STP27N3LH5), we see the SOA chart below with the two operating points marked with stars. Basically, what we’re saying is the green star works and the red star fails. Both stars are in the “safe” area and you’d be forgiven in thinking the red star should represent a more robust operating point. Take a minute to study the SOA plot while studiously trying to ignore the typo. What’s a Sinlge pulse? But, let’s not digress.
For this part, ST does not show the DC test result. Why is that? Is it because the DC performance was outstanding and they did not want to brag? Maybe. Maybe not, but here we are, digressing again.
What’s with the ascending line labeled with “Operation in this area is Limited by max RDS(On)”. Beyond questionable syntax, could this note have a relation to the reliable parallel-FET performance? [Insert an image here of Jon and Ken looking at each other with puzzled expressions.]
The note means the SOA performance might be good in that area, but we’ll never know because the FET RDS(On) will not allow the control loop to drive us into that region. Put another way: the control loop will overdrive the FET gate to try to operate in that region. Aha. In the 1V@18A case, the FETs are not operating in the high-stress linear mode—their channels are either fully enhanced or close to fully enhanced and the FETs are forced into sharing current.
‘Linear mode.’ There is a phrase to strike sheer terror into the hearts of engineers. For the 12V@1.5A case, the FETs are definitely forced by the control loop into the high-stress linear mode. That’s why they fail. Shall we discuss linear mode operation in more detail? Sure, if you want us to, we will go into infinite, tedious detail in a follow-on blog.