How do advanced design changes impact power integrity? This is a question often encountered by power-integrity aware IP block designers. And here is where a front-end analysis environment such as Anasim's PI-FP is most useful. We introduced PI-FP's key characteristics in a prior publication years ago (See Reference 1). There, we described how a true physical simulation environment assists chip floor planning. We looked at on-chip capacitor allocation and explored active noise regulation. In this example, we look at load current modulation.
Clock edges in a synchronous IC tend to display large supply current spikes. These spikes are a load to the local power grid and result in significant droop or dynamic voltage drop. Designers often wonder if they may use advanced techniques, such as intentional clock skew, to alter such loads. The technique has much intuitive appeal: distribute gate switching to reduce supply load coincidence.
In this simple example, we look at one such modification to a clock domain and its PI impact. Clock-edge current load is split in two by a partitioned clock domain and designed clock skew. Supply current consumption is "spread out" in time, and we look at PI degradation for both cases. What do we expect to see? What can we learn about differences between PI-FP and a non-physical IR Drop simulation?
Power Grid and Load Block
Figure 1 below shows a chip power grid connecting through package pathways to a supply point. The load block connects to the power grid within an area bounded by supply connections. Abstract power bus information, such as bus widths and separation, defines the grid. Electrical information relevant to PI, such as Inductance, Capacitance, and Resistance, are also captured. Note, as a floor planning environment, that PI-FP captures key circuit physical aspects.
Physical schematic of power grid and load block in PI-FP
Figure 2 shows load block physical and electrical aspects captured in PI-FP. Note a 'v/c' fraction in both schematic views. This represents a check for physicality: speed of EM wave propagation in the grid. Any power grid without inductance violates this law of physics. Resistive grids beat c, the speed of light (no matter what tool vendors tell you)!
Load block (block1) physical and electrical aspects
Single peak block load current.
Let's first look at a load condition where logic circuits switch with a single clock edge. The supply current spike is a single triangular load peak as seen in Figure 3. Clock skew and jitter produce anything from a Gaussian to a Bathtub distribution of edges in time. But this approximation suffices for our simple 'what-if' analysis.
Figure 3 illustrates the load current peaking at 0.6ns. PI-FP permits easy manipulation of block load current waveforms in the GUI popup shown.