Peak Currents and Maximum Noise Amplitude
In a Power Integrity (PI) world dominated by i·r drop, it is common to relate peak noise in a macro power grid with peak current drawn from the supply. After all, if noise is i·r, then peak noise must correspond with peak i, yes? But is this really true? Is a power grid represented with good accuracy as a complicated mesh of resistances? We answer the first part of this exploration – the non-correlation of peak noise with peak current – in this experimental study.
Consider any interconnect segment of a macro block power grid. What are the key aspects of its electrical behavior relevant to PI? It exhibits resistance to the flow of current through it. But it also exhibits electrical inertia, a property termed inductive reluctance, that impedes change in its electrical current flow. And, an electrical capacitance, associated with the wire, reacts to any change in its electric potential. Two of these electrical aspects lead to noise, or variation in its electric potential, while the third helps mitigate it.
The electrical picture isn't all that simple! It's not just a resistance r, though we may like it so.
Equations that capture the behavior of such power grid (PG) interconnect elements aren't simple either. Equation (1) in this 2006 paper represents noise in an interconnect segment, modeled as a lumped resistance in series with an inductance, as i·r + L·di/dt. Hidden within this simple relation are more complexities.
Say instantaneous current i is a sinusoidal wave. That makes the term di/dt a cosine wave, one shifted in phase by 90o from the original sine. The di/dt component peaks when the sine wave is rising, or falling, at zero amplitude, and not at the peak of the sine. Besides, di/dt is zero at the peak of the sine wave. In simple words, peak instantaneous current and the peak rate of change of current do not coincide. The equation for noise thus combines an in-phase value, i·r, with a 90o shifted value, di/dt, which result does not correlate well with the stimulus in this case.
A continuum simulation example lights our way ahead.
A physical schematic view of a chip power grid and associated PDN [PI-FP]