Spatio-temporal aspects of Dynamic Voltage Drop (DVD)
A recent Planet Analog article, Non-correlation of Peak Noise and Peak Current, discussed the complexity of reactive and resistive noise that combine to form dynamic voltage drop in a chip power grid. In that experiment, we saw how DVD varied with load waveshape, while peak load current stayed the same. Another experiment, exploring local power grid resonances, demonstrated DVD variance with changing load frequency. Again, peak load current remained constant, while spatial relationships between load currents and capacitance determined resonances. In the following experiment, we explore DVD variance with another aspect of PDN load currents. Here, we explore the temporal relationship between load vectors: time/phase delays between load maxima.
Why is this important to DVD optimization and sign-off? I have come across repeated instances in the past where chips have failed at the prototype stage. These complex systems incorporated numerous IP cores, DSP's and baseband processors, which share their PDN. The failure mode was invariably an activation regimen for the cores that produced large supply current spikes. And, these chips had passed through back-end sign-off verification for power integrity. Complex, nanoscale SoC's of the present are no doubt prone to such potential failures.
Besides, the EDA industry has sold a limitation, analysis sans vectors, as a feature for a decade or more. They've trained hapless customers to ask: "Do you have a Vectorless Analysis Engine?" Sounds fancy, does it not? But what's a load vector without its timing and rate-of-change-with-time attributes? A stator, fit for multiplication with - Aha, that's (i⋅r drop ) the reason! - a static resistance value. Vectors also won't work correctly with a chip PDN model that breaks the speed of light. More limitations - that fit exceedingly well with an ingenious marketing tactic. I wrote about a necessary transition in 20084 !
I think it is crucial to investigate whether such approximations lead to accurate, dependable results.
Figure 1 below shows a complete PDN from a supply through board and package pathways and a chip power grid. Load blocks (charge consuming circuits) in purple, shown on the lowermost layer, connect to the chip power grid. They form distributed area loads, as it is in actual integrated circuits. Distributed capacitances, shown in parrot green on a layer above the load circuits, also connect to the chip power grid. The setup replicates the local resonance exploration experiment.
Note adjacent loads I1 and I3 in the PDN schematic. An identified resonance in this region of the chip PDN is near 5GHz. This resonance occurs when both I1 and I3 stimulate the PDN with the same load current wave. In this experiment, we vary the time delay between the two respective load waves. This is shown in Figure 2, which lists load stimulus ASCII files displaying 90° and 180° phase shifts for load current. Both peak load current and load spectral content remain unchanged from those at resonance.
Full PDN representation including chip/package power grids and board components.
Half-Sine 100mA load waves delayed by 50ps and 100ps (90o & 180o for a 200ps period).