Dynamic voltage drop or DVD in a chip power grid segment is in essence transient noise. It is a complex superposition of various noise components of a typical chip power grid that reduces available power supply differential. DVD is a key measure of chip power integrity, and requires careful inspection during chip design. It is a sign-off gating aspect of chip power delivery.

Measured at points of interest on the grid, DVD is distinct from static (IR Drop) voltage reduction. But this distinction blurs at times depending upon the analysis method adopted. A review of such methods is thus useful - both to comprehend DVD and to recognize its derivation at present.

It is perhaps best to begin at the beginning as I've done in Chapter 1 of Power Integrity Analysis and Management for Integrated Circuits. In that chapter, 'Power, Delivering Power, and Power Integrity,' I delve into fundamental constituents of supply noise, introducing the *3 R's of Interconnect*: Resistance, Reactance, and Resonance. Chapter 2 details the response of power delivery networks (PDN's) to load stimuli. A separation of transient (AC) and static (DC) noise becomes clear through such response. The analysis described therein captures circuit behavior in the TIME domain. Figure 1 displays an example.

**Figure 1**

**Time domain simulation of supply noise at the chip-pkg interface.**

But such capture as in Figure 1 are *nodal* simulations: supply voltage variation at a circuit node with respect to an ideal ground. A chip is a two dimensional surface. Voltage variations across its power grid are typically captured as shown in Figure 2.

**Figure 2**

**IR Drop snapshot on segments of a chip power grid (See Reference 1).**

With X and Y dimensions displaying the actual chip power grid, color shows voltage variation in the IR Drop snapshot of Figure 2. Note that spatial variation of noise provides useful information though time variance is absent. One sees the development of areas of greater current density and corresponding voltage reduction. Yet, such a snapshot captured hides many inadequacies as discussed in **Reference 1**. Given the computational complexity of such analysis on a ULSI chip, software tools reduce power grid segments to their base resistance, for example. Such reduction in IR Drop analyses loses at least two rigors of the *3R's of Interconnect*.

**Frequency Domain Analyses**

PDN's on printed circuit boards (PCB's) and chip packages are also analyzed in parallel in the FREQUENCY domain. Lumped approximations for PCB aspects, and impedance measurements, facilitate such analyses. Chapter 5 in **Reference 1** discusses this in detail and describes the *target impedance* design method often pursued. Through lumped abstractions for electrical behavior, one can also correlate frequency domain characteristics with time domain behavior. Figure 3 illustrates such correspondence.

Note that transient noise resulting from the excitation of PDN's by load spectral components at impedance peaks are called 'Droops.' The term 'Voltage Drop' is usually reserved for static reductions in voltage or to averaged noise levels.

Circuit-accurate responses and droops (1st, 2nd etc.) are in Figure 1. Figure 3 illustrates only the correspondence between time domain responses and frequency domain aspects.

**Figure 3**

**Hand-drawn sketch of frequency domain impedance variation and corresponding time domain voltage noise responses. See Reference 2.**

**Figure 4**

**Frequency domain design of a board PDN. See Reference 2.**

But frequency domain analysis abstracts electrical behavior, including *resistance, reactance,* and *resonance,* to a single aspect: **impedance**. It ignores vector phase relationships and surface noise wave propagation and interference. Besides, impedance measurements are made at a node, just as time-domain noise variance is measured at a circuit junction. Hence the applicability of this method to a surface, attached to distributed and varied electrical components, such as a chip power grid, is rather limited. And, as established in theory in Chapter 5 of **Reference 2**, the target impedance of a PDN is not a reliable indicator of maximum possible noise.

Nevertheless, frequency domain analyses continue to assist PCB and package design. Figure 4 illustrates a design procedure that attempts to meet a given impedance target. A combination of the frequency response of a chip model and the characteristics of the board PDN results in an impedance peak at
∼
109 MHz. Observe the impedance characteristic of the chip: it is a simple capacitor-resistor model. Its impedance falls linearly on a log-log plot as frequency increases, flattening out to its effective series resistance at the end of the range. Further analysis in **Reference 2** shows that package inductance plays a large role in determining the combined impedance peak as seen at the board/chip interface. An extension of the same finding establishes that local, on-chip, power grid impedance thus depends upon inductance to on-chip decoupling capacitance.