The internet-of-things, or IoT, a fast-developing application space, is forecast to grow to 50B devices by 2020. Figure 1 illustrates a smart home segment of this market. Devices communicate with each other and through a smart hub with the internet. These devices need complex mixed-signal chips for sensing, processing, communications, and even energy harvesting. Since most IoT devices are not tethered, such chips must meet ultra-low power  and low-cost constraints.
A prevailing assumption in the industry, EDA in particular, is that IoT chips are less of a challenge. Technology and IP integrated are well known. The chips are not leading edge in the fabrication processes used. Tools that met the needs of prior fabrication processes hence suffice to meet the needs of IoT chips. It is just a matter of designing to the specific application.
Nothing could be farther from the truth when one considers power integrity (PI)! One of the first challenges with dynamic voltage drop I've encountered was in an embedded heart-rhythm monitoring chip. A combination of its fabrication process and operational constraints led to this difficulty. Small form-factor, low-cost, and ultra-low power combined to impact chip DVD and reliable operation.
As described ahead, many challenges arise when meeting the constraints of IoT chip design. But there are solutions: front-end PI analysis and optimization being the most promising.
Figure 1: A connected network of devices, smart hub, and the internet (Image: ComLSI)
Power and Power Management
Power is a critical aspect of an IoT chip. The devices must operate for days to years on battery power or on energy harvested from their environment. Such chips must thus consume the lowest possible power in the application space. And meet this need despite a wide variance in conditions of deployment . These constraints, and their energy storage form factor, limit IoT chips to between nW and mW of power consumption.
Figure 2: Power limitations (nW to mW) of IoT devices based on energy storage 
This power limitation requires the use of all circuit and system techniques that cut power. Circuits operate at the lowest possible voltages to conserve energy . When required, they operate at higher voltages in burst mode. Small, efficient DC-DC converters enable such circuit functionality. Many circuits operate in low-swing mode. Power gating manages supply to most IP blocks that do not need to be always-on. Form-factor limitations compel the use of small linear regulators for such power management.
Figure 3: Block diagram of a TI SimpleLink CC26XX IoT processor 
These circuit and system techniques result in fragmented and weak power supplies within IoT chips. They also reduce available noise margins for circuits within. Low-cost fabrication processes limit available metal layers for low-impedance power grids. Limited on-chip and package decoupling capacitors further degrade IoT chip power grid robustness.
A voltage regulator isolates a chip IP block from power grid noise. It often performs a dual function of power gating the IP block. But it also generates significant inrush current load on a chip power grid when the IP block awakes. Besides, an isolated block does not support a chip power grid with its intrinsic decoupling . Thus, IP block isolation, while beneficial in power reduction, can cause significant local PI degradation.