Voltage-Dependent Decoupling Capacitance
The most common approach to PI management, particularly for droops and other dynamic supply differential variations, is the addition of on-chip decoupling capacitance. Capacitance, local to a load circuit that draws transient supply current, can help fulfill transient charge demand. But since this capacitance is a “reactive” circuit component, charge is provided in reaction to changing voltage, where i(t) = C(dv/dt). Capacitance thus reduces voltage droop by providing charge, but only if a droop has occurred.
Now consider a voltage-dependent capacitance element, with capacitance that varies with voltage across the plates of the capacitor structure, as illustrated in Figure 1.
Voltage-dependent capacitance function.
Since capacitance C is a linear function of applied voltage V, charge Q changes quadratically. Hence, in a voltage-dependent capacitance, the rate of change of charge with voltage dQ/dV is in part proportional to kV. At full charge, therefore, charge depletes at a faster rate (C0 + kV > C) in such a capacitor as compared with a constant capacitor. Hence, for the same quantity of charge ΔQ removed, voltage reduces less in the voltage-dependent capacitance case. This may also be understood as follows: at a given operating voltage Vdd, let charge stored be C1Vdd for a constant capacitor.
For a quantum of charge ΔQ removed, from a voltage-independent capacitor, let the removed charge be reflected by a change in voltage to Vn1. In the voltage-dependent case, the same ΔQ removal results in a voltage Vn2, and a capacitance Cn2 that is lesser than the voltage-dependent capacitance V2 at Vdd. By charge conservation, with ΔQ small, C1ΔV1 ≈ C2ΔV2, where ΔV is the reduction in voltage, and since C2 ( = C0 + kVdd) is greater than C1 (to store the same total charge with quadratic charging), >ΔV2 is smaller than >ΔV1. This leads to an approximate relationship:
As seen in Figure 2, capacitance varies significantly with voltage in MOSFET devices operated in their accumulation-depletion mode (right side of graph in the figure). Devices can therefore be engineered and biased to display voltage dependence at a given operating supply voltage, though this characteristic may be bandwidth-limited. MOSFET devices operated in the accumulation-depletion region also demonstrate lower gate-oxide leakage than devices operated in the traditional mode of channel inversion. This provides an incentive toward biasing devices in this manner, and has led to the wide adoption of this decoupling capacitance configuration in ICs. (Note: Chips from the 130nm node down at Intel Corporation are believed to employ such on-chip decoupling capacitance.)
Capacitance with gate voltage for MOSFET devices in a deep-sub-micron fabrication process from inversion to accumulation.
Charge and Energy in Voltage-Variable Capacitance
Charge and energy contained within capacitors exhibiting the behavior illustrated in Figure 2 may be derived as follows:
Since C = C0 + kV, charge Q for a voltage-variable capacitor is:
assuming V = 0 when Q = 0. This reduces to Q = CV for k = 0, and Q = ˝ kV2 = ˝ CV for C0 = 0. Charge contained within the voltage-variable capacitance rises quadratically, and is one-half of the charge in the voltage-independent capacitance case when the base capacitance is zero. Hence C0 and k must be chosen to ensure that the total charge stored is the same in both cases.
Energy within the voltage-variable capacitance may be similarly derived as follows, from the incremental work done for an incremental charge:
Again, for k = 0, the above expression reduces to the known expression for energy stored in a constant capacitor. Interestingly, for C0 = 0, and k = 2C/V, chosen such that the total charge stored is the same as in the constant-capacitor case, the expression for energy in the voltage-variable capacitance yields a value of (2/3)CV2, or one-sixth higher energy as compared with a constant capacitor.
Furthermore, for the voltage-dependent capacitance case discussed in the paragraph above, supply voltage noise that manifests may be compared as:
Nevertheless, the impact to power integrity with voltage-variable capacitance is a complex phenomenon not easily modeled as shown in Figure 1 or derived as in Equation (1). The change in device capacitance with voltage as seen in Figure 2 arises from the non-ideal charge distribution within semiconductor material. As the applied bias is increased into the region where the device exhibits a positive voltage coefficient, the effective distance between charges on the two gate-oxide-isolated sub-parts of the device decreases from its unbiased value. This results in a reduction in the effective electrical separation between the “conducting plates” of the device, thus increasing its capacitance, since capacitance is given by C = єA/d.
Work is done in this change produced in the device electrical characteristics, and the device stores charge and energy in the form of this change of its intrinsic electrical nature. A macroscopic analogy is the behavior of a parallel-plate capacitor where the plates are retained separated from each other by springs that attach them to rigid surfaces. As differential charge on the plates is increased, the plates are attracted towards each other, decreasing the distance between them and increasing effective capacitance. Simultaneously, energy is also stored in the displacement of the springs produced by the motion of the plates, therefore requiring an electrical-physical model for analysis purposes.
The preceding discussion serves to emphasize the need for true-physical modeling as discussed in prior chapters. In voltage-dependent decoupling capacitance, approximating the effective capacitance value by a fixed, distributed capacitance serves to provide reasonably accurate estimates of noise sufficient for floor planning purposes. As is most often the case, there is no substitute for silicon verification of circuit functionality and noise in any new fabrication process or device bias configuration. On-chip decoupling capacitance effect, given its voltage-variability, must therefore be validated in silicon, and device behavior captured and modeled as derived from physical behavior.
- Bennett, D., and R. Nair. 2006. How to dynamically mitigate power supply noise and active noise regulation., Online articles, Active Noise Regulation .
- Nair, R. 2007. Voltage Droop Suppressing Active Interposer. U.S. Patent no. 7291896, November.
- Nair, R. 2008. Voltage droop suppressing circuit. U.S. Patent no. 7378898, May.
- Wikipedia, The Free Encyclopedia. 2009., various pages.
- Nair, R., and De, V. K., 1999. Device and method for controlling voltage variation, U.S. Patent application no. 09/460,742, December 14, pub. no. 2003/0058022.
- Nair R., and Bennett, D., 2010 Power Integrity Analysis and Management for Integrated Circuits, Pearson/Prentice-Hall, ISBN 978-0-13-418595-8, April