eGaN Technology Physics of Failure
The previous installment in this series focused on the physics of failure surrounding thermo-mechanical reliability of EPC eGaN wafer level chip-scale packages. A fundamental understanding of the potential failure modes under voltage bias is also important. This installment will provide an overview of the physics of failure associated with voltage bias at the gate electrode of gallium nitride (GaN) field effect transistors (FETs). Here we look at the case of taking the gate control voltage to the specified limit and beyond to investigate how eGaN FETs behave over a projected lifetime.
eGaN FET Basic Structure – Lateral Enhancement Mode
The basic lateral eGaN transistor structure is shown in Figure 1. The gate (G), source (S), and drain (D) terminals are arranged like a typical field effect transistor. The device is formed starting with a silicon wafer followed by growth of a gallium nitride heterostructure, which results in an enhancement mode device which is normally off (non-conducting) with no bias applied .
The conducting channel is formed by growing a thin AlGaN layer on top of the high resistance GaN layer. The AlGaN to GaN interface creates a strained piezoelectric effect, where a two-dimensional electron gas (2DEG) of abundant high mobility electrons exist. The gate electrode forms a depletion region in the 2DEG to block the conducting channel in the off-state. Protection dielectrics and metal routing form the top layers of the device.
The FET is enhanced to the conducting on-state with the application of a positive voltage at the gate electrode, similar to the operation of a silicon n-channel enhancement mode power FET. The power FET is formed by connecting many of these basic cell structures in parallel.
eGaN FET basic cell structure.
Figures 2 and 3 show the gate-to-source bias (VGS) transfer curves and on-state resistance (RDS(on)) vs. gate voltage representing a typical eGaN FET . The voltage level to achieve turn-on threshold and subsequent transconductance as a function of drain current is shown in Figure 2. Figure 3 shows the conducting channel is fully enhanced near a gate voltage of 4 V, as the corresponding on-state resistance remains relatively flat beyond that point. Absolute maximum gate-to-source voltage of 6 V ensures safe operation.
Transfer curves for EPC2016C
RDS(on) vs. VGS at various currents for EPC2016C