eGaN® Stress Test Qualification and Capability
The first two installments in this series reported in detail on field reliability experience of Efficient Power Conversion (EPC) Corporation’s enhancement-mode gallium nitride (eGaN®)
FETs and integrated circuits (ICs). The excellent field reliability of eGaN® devices demonstrates stress-based qualification testing is capable of ensuring reliability in customer applications. In this installment we will examine the stress tests that EPC devices are subjected to prior to being considered qualified products.
EPC products are considered production ready only if they are able to withstand a rigorous set of stress-based qualification tests, while continuing to operate within datasheet specifications. To ensure product reliability in end-user applications over expected operation lifetimes, stress tests are used to accelerate potential failure modes. All EPC products are qualified according to Joint Electron Device Engineering Council (JEDEC) stress tests, which are intended for power FETs, ICs, and chip-scale packaging. EPC stress test qualification can be grouped into three main areas, intrinsic die, package environmental, and board-level reliability.
Table 1 below provides an overview summary of qualification test results including sample size, equivalent device hours, and statistical estimate of failure rate. Additional qualification data for specific products or product families can be found on the EPC home page: eGaN® FET Reliability .
The sections that follow will go into more depth explaining the qualification stress tests and objectives.
Summary of Composite Upper Bound Failure Statistics
Intrinsic Die Qualification
Figure 1 shows the basic structure of the eGaN® power transistor. The device is a three terminal lateral structure, in which current flows from source to drain along a two dimensional electron gas (2DEG). Normally, the 2DEG is depleted under the gate resulting in an off state condition. When a positive bias voltage is applied to the gate terminal, the 2DEG is enhanced and fills in under the gate completing the conductive path from source to drain.
eGaN® power transistor basic structure
Voltage and temperature are most commonly used to accelerate stress conditions within the die. Elevated voltage and temperature over many hours can be translated to predict reliable operation in terms of years within customer application circuits. High Temperature Gate Bias (HTGB) is the standard test used to examine the reliability of the device under applied gate stress. The device is set to the off state (drain shorted to source) with gate-source bias voltage (VGS) ≥ 80% maximum rated, and maximum rated junction temperature (Tj) applied.
High Temperature Reverse Bias (HTRB) is used to evaluate reliability in the off state under high drain bias condition. The device is biased in the off state (gate shorted to source), with drain-source voltage (VDS) set to ≥ 80% maximum datasheet rating at maximum Tj. All device parametric parameters including leakage current, threshold voltage, and on-state resistance (RDS(on)) are monitored for device stability.
EPC has accumulated a large set of HTGB and HTRB data demonstrating the intrinsic reliability of eGaN® FETs and ICs. The data shows these devices are on equal footing or even more reliable than their silicon counterparts. In fact, military and space (radiation hardened) applications are on the forefront of GaN adoption, which would not be possible without a high level of confidence in reliability standards established.