Editor’s note: I am pleased to bring you another edition of RAQ by Umesh Jayamohan
Question: Why are there all these power domains for high speed ADCs?
Answer:Today’s radio frequency analog-to-digital converters (RF ADCs) have come a long way in terms of sample rates, as well as serviceable bandwidths. They also pack in a lot more digital processing and have increased in complexities when it comes to power supplies. With that said, why are there so many different power rails and domains in today’s RF ADCs?
To understand the proliferation of power domains and supplies, we need to take a trip along ADC history lane. Back in the days when the ADC was just that, an ADC, the sample speeds were slower—in the 10s of MHz—and the amount of digital content was small to nonexistent. The digital portion of the circuit primarily dealt with figuring out how to transmit the bits out to the digital receive logic—either an application-specific integrated circuit (ASIC) or field programmable gate array (FPGA). The process node used to fabricate these circuits was a higher geometry, around 180 nm or more. You could extract adequate performance from a single voltage rail (1.8 V) and just two different domains (AVDD and DVDD for analog and digital domains, respectively).
As silicon processing technologies improved, transistor geometries reduced, meaning one could pack more transistors (in other words, features) per mm2. However, the ADCs were still expected to achieve the same (or better) performance as their earlier generation counterparts. Now, the design of the ADC had taken a multifaceted approach where:
- The sample speeds and analog bandwidths had to be improved
- The performance had to be the same as or better than previous generation
- There is more on-chip digital processing to aid the digital receive logic
Let us further discuss each of these features and how they pose challenges to the silicon design.
The Need for Speed
In CMOS technology the most popular way to go faster (bandwidths) is to go smaller (transistor geometries). Using finer geometry CMOS transistors results in reduced parasitics, which aid in the transistor’s speed. Faster transistors mean wider bandwidths. The power in digital circuits has a direct relationship to the switching speed, but a square relationship to the supply voltage. This is shown by the equation below:
P is power dissipated
CLD is load capacitance
V is supply voltage
fSW is switching frequency
Going to finer geometries allows circuit designers to implement faster circuits while maintaining the same power per transistor per MHz as the previous generation. As an example, take AD9680 and AD9695, which were designed using the 65 nm and 28 nm CMOS technology, respectively. At 1.25 GSPS and 1.3 GSPS, the AD9680 and AD9695 burn 3.7 W and 1.6 W, respectively. This shows that for the same architecture, give or take, the same circuit can burn about half the power on a 28 nm process as it did on a 65 nm process. The corollary to that is you can run the same circuit at twice the speed on 28 nm process, as you did at 65 nm while burning the same amount of power. The AD9208 illustrates this to a good extent.
Headroom Is Everything
While the need for sampling wider bandwidths has necessitated the move to finer geometries, the expectations on data converter performance—like noise and linearity—still stand. This poses a unique challenge to analog design. An unintended side effect of going to smaller geometries is the reduction in supply voltages. This greatly lowers the headroom required to develop the analog circuits needed to operate at the high sample rates and maintain the same noise/linearity performance. To circumvent this limitation, the circuit is designed with different voltage rails to provide the required noise and linearity performance. In the AD9208, for example, the 0.975 V supply provides the power to the circuits needing the fast switching. This includes the comparators and other associated circuitry, as well as the digital and the driver outputs.
The 1.9 V supply provides power to the reference and other bias circuits. The 2.5 V supply provides power to the input buffer, which requires the high headroom to function at the high analog frequencies. It is not necessary to have the 2.5 V supply for the buffer; it can operate at 1.9 V as well. This lowering of the voltage rail will result in degraded linearity performance. With digital circuits, there is no need for headroom as the most important parameter is speed. So, digital circuits usually run at the lowest supply voltage to take advantage of the CMOS switching speed and the power dissipation. This is evident in the newer generation ADCs where the lowest voltage rail is as low as 0.975 V. Table 1 below shows some common ADCs across generations.