Current Feedback Amplifiers (CFA) provide the highest Large Signal BandWidth (LSBW), but relatively poor DC precision. The elements creating that poor DC precision will be detailed here. Of particular interest is the CMRR error in the CFA design. That low CMRR arises from the input buffer gain being <1.0. The more recent Fully Differential Amplifiers (FDA) offer both CFA and VFA versions. The CFA based versions will also have poor DC accuracy while more recent “precision” VFA based FDAs can provide much improved DC accuracy. Those VFA-based FDAs do come with some added DC error sources beyond the typical op amp terms that will be described here.
DC accuracy for Current Feedback Amplifiers (CFAs)
The CFA found its true calling in low gain video line driving and differential xDSL line drivers (ref.1), where DC precision is a minor consideration in, what are often, AC coupled output designs. The architecture does not lend itself well to low nominal output DC errors or drift. Once an amplifier starts to deliver reasonably low nominal 25oC DC errors, the next layer to consider are their drift terms. All CFAs are constructed with a unity gain buffer from the V+ input to the V- input. That buffer will show these DC errors:
- Input offset voltage and drift
- Non-inverting bias current and drift
- Inverting bias current and drift
- CMRR (which arises from the buffer gain being <1.00000).
Even with considerable effort (ref. 2), the best reported input offset voltage drift is a nominal 1μV/oC with a 5μV/oC max., where very few CFAs even specify a max. offset voltage drift. The two input bias currents for a CFA are essentially the difference between base currents arising from mismatched NPN and PNP βs. The mechanisms are completely different at the detail level for the two input bias currents, hence they are unmatched both nominally at 25oC as well as in their temperature drifts. The output DC error drift is often dominated by the inverting bias current drift times the feedback resistor (Rf). Even one of the most recent single channel CFA devices, the THS3491 (ref. 3), specifies only a nominal Ib- drift of -116nA/oC (with no min/max – but with the first ever CFA drift histograms, page 17, ref. 3). CFA devices require a narrow range of feedback resistor values (Rf) for stability. Using the THS3491 recommended 576Ω, for the QFN package (Av=+5V/V), translates to 576*(-116nA/oC) = -67μV/oC at the output – hardly a DC precision device. And, since the two input bias currents are not matched in either 25oC nominal nor drift terms, bias current cancellation techniques are not applicable (ref. 4).
Going one more step, the reported CMRR for a CFA device arises from the buffer gain being slightly <1.0000 (ref. 5, page 36). In the four equal-resistor, differential-to-single-ended configuration, it is this slight gain loss across the input stage that gives rise to an output signal when the two inputs are driven from a common mode source. Most CFA input buffers are open loop, where a typical buffer gain of 0.996 would create a CMRR spec of 48dB via equation 1 (with α being buffer gain in V/V).
Stand alone, open loop buffers, specify a DC gain that is very load dependent due to their finite DC output impedance (Ref. 6). The input buffers used in both CFAs, and very high slew rate VFAs (Table 3, Ref. 7), see a no-load condition since the overall loop in both cases drives their output (error) current(s) to zero. The buffer output at the inverting CFA pin cascodes the error current to the current mirrors, while also forcing the inverting node voltage to follow the +V input. Being part of the overall CFA feedback loop means the error current in this buffer output is driven to zero by the high DC loop gain, this is identical to saying the buffer sees a no-load condition. This loop gain induced, no-load condition holds the buffer DC gain very constant vs. external resistor settings at just below 1.000.
This “CMRR” effect in the CFA will “contract” the gain from ideal. This is easy to see in a simple non-inverting unity gain buffer application where the input stage buffer gain reduces the gain from V+ to V- slightly below 1.0000 while the LG/(LG+1) gain compression reduces it slightly more to the output voltage. The four equal-resistor differential-to-single configuration can be used more generally to probe the polarity and magnitude of the error signal across the input stage due to a common mode input voltage swing. This test case produces a very small output voltage swing, reducing the input referred error due to that small Vout divided by the Loop Gain (LG), to an inconsequential level relative to the input error produced by the CMRR effect. That CMRR error should produce a +/-μV/Vcm input error voltage that then gets gained up by the Noise Gain (NG) to add to the output error (ref. 8).
The test of Figure 1 is driving a 1Hz input square wave into the 4 equal-resistor circuit and is looking for the polarity and magnitude of the square wave at the input error voltage sensing output. This positive first input signal will generate a negative first error signal (including the -1 in the dependent source) if the CMRR effect is a -μV/Vcm (or contracting gain) effect – as it is for all CFA devices. This error voltage square wave is sitting on top of the static DC error terms for the low power OPA684 (ref. 9) used in Figure 1. This 1.615mVpp input error swing, for a 1Vpp Vcm test signal (at the V+ input pin), gives -20*log(1.615mV/1) = 55.8dB CMRR. This relatively higher CMRR for the OPA684 CFA (vs. a more typical 48dB CMRR) comes from the closed loop input buffer design and approximately agrees with the datasheet specifications. Solving eq. 1 for the buffer gain shows that the OPA684 model is delivering a nominal α=0.9984V/V.
While there are no true “precision” CFA op amps, there are better and worse devices. Making a simple sort on maximum 25oC input offset voltage, recognizing very few devices specify a max. offset drift (and many devices physically show an output DC drift dominated by the inverting bias current drift), will yield the rough sort of Table 1. In this range of max. offsets from 2mV to 5mV max, a secondary sort in each offset value ranked them in ascending max. 25oC supply current. In each max. input offset value, this ascending supply current roughly sorts the devices in descending input voltage noise and ascending slew rate. To get newer devices, this table also screened out:
- Max. input Vos > +/-5mV
- Output Headroom >2.0V
- If both disable and non-disable versions, only disable version shown.
- Obsolete devices
Turning back to the very high slew rate VFA devices, using two open loop input buffers (table 3, ref. 7), it might be reasonable to expect those to also show a very slight gain compression (-μV/Vcm) in their simulation models due to the CMRR effect. The transistor based AD8057 (ref. 10) model available in the TINA library (ref. 11) does indeed contract as shown in Figure 2. Many of the more “macromodel”-based devices (in Table 3, ref. 7) show a positive +(-μV/ Vcm effect in this same simulation test. This simulated input error voltage swing, of 0.31mVpp for a 1Vpp Vcm input swing in Figure 2, solves to a 70dB CMRR. This result closely matches the AD8057 CMRR plot (Figure 30, ref. 10) but not the 60dB specification.
Looking at the other types of high speed VFA devices (ref. 7), it is unclear if they should show a + or – μV/Vcm error term and their models seem to essentially give random polarities (where some models have reversed polarities from their original to more recently updated versions). Some sources (slide 9, ref. 12) suggest this CMRR error should be a bipolar Gaussian distribution centered on 0 μV/V. But that implies an average CMRR of infinite dB? There is possibly more modelling work that could be done on this CMRR error term in the wider range of VFA op amps.