DC Accuracy for High Speed Fully Differential Amplifiers (FDAs)
These FDAs come in both CFA and VFA types. The CFA-based versions will have phenomenal slew rates but relatively poor DC precision terms. For the wide range of AC-coupled signal path application using CFA-based FDA solutions, this poor DC precision will not matter. The most troublesome term would be the input offset current drift specification – typically a missing spec. for these types of devices. Table 2 shows a thorough DC error specification (ref. 13) that is notably silent on Ios drift – likely pretty poor looking at the range on 25oC Input Offset Current.
Turning now to the more “precision” VFA-based FDA devices (Table 3 below), these have the usual input offset voltage (Vos) and current offset (Ios) errors along with a range of other errors arising from the two feedback networks not being exactly matched - and due to the common mode control loop that is acting to hit a desired output average voltage. Only considering DC issues here, first assume the two feedback resistors and divider ratios to the inputs are exactly matched – as shown in the example of Figure 3 using the precision RRO, NRI THS4551 (ref. 14) with 4 equal 10kΩ resistors and a grounded Vocm input on +/-2.5V supplies. Centered gaussian DC errors (like Vos and Ios) are often specified as +/- 1 δ for the typical value. That bipolar value, is then assigned a polarity to include in the nominal simulation model. The full bipolar min/max error range and drifts are available in the datasheets (ref. 14). Figure 3 shows a simple DC setup with measurement probes before the DC simulation in Figure 4 where those numbers will mask the circuit underneath.
Equal R, THS4551 FDA nominal DC error test simulation
And then running the DC operating point simulation shows these error terms built into the nominal model (ref. 15).
DC operating point errors for the precision THS4551 FDA
Starting with the common mode voltages, the output common mode shows a +1mV positive offset from the 0V input at the Vocm pin. This matches the magnitude of the typical specification of +/-1mV (ref. 14, page 9). This device is typical in that the common mode control offset error is lower with the input control pin driven vs. when it is floating. The floating input Vocm offset (from mid-supply) is typically +/-2mV on this device. This output CM offset is usually of negligible concern in driving ADCs that show some tolerance on their input common mode voltage range (when specified) far exceeding these <+/-20mV output Vocm errors.
This Negative Rail Input (NRI), PNP input stage device, will have input bias currents that flow out of the input pins. That average value in Figure 4 of 0.9934μA closely matches the typical 1μA in the data sheet (ref. 14, page7). This input bias current specification is uni-polar out of the input pins for this NRI device. One new aspect to the FDA is that this common mode input bias current shifts the “input” common mode voltage from the output common mode that is being controlled by the common mode control loop. The 5.47mV input common mode voltage shown in Figure 4 has shifted up from the 1mV output common mode and correctly splits the available .993μA common mode current into the Rg2 path to ground, and then the Rf2 path back to the output 1mV common mode voltage. This input Vcm level shift is approximately the output Vcm voltage + the input Ibcm current times the Rf||Rg impedance looking out the two input nodes.
The differential output offset is a combination of the input offset voltage and the effect of mismatched input bias currents (Ios). The nominal +50μV input offset voltage is gained up by the Noise Gain (NG) = 1 +Rf/Rg to the output while the differential offset current (Ios) adds an Ios* Rf term to that. Since this Ios is differential, the output common mode control loop does not come into play and the typical differential input virtual ground is used to pass this term to the output times just the Rf value.
The THS4551 model (ref. 15) sets the typical Vos polarity to be a 50μV rise from V+ to V-. This will produce an output of +100μV for Vo_diff (Using the (Vo+) – (Vo-) voltmeter in Figure 4). This simulated output offset is then reduced superimposing the nominal model polarity of the Ios term. There, the 9nA Ios is higher on the non-inverting input pin than the inverting, approximately reducing the 100μV output due to Vos by the 9nA*10kΩ ≈ -90μV yielding close to the simulated value of +11μV. Again, the model assigns nominal values and polarities while the full range shown in the datasheet (ref. 14) should be used for output differential offset min/max analysis.
Temperature drifts, on the input bias current average value, will simply shift the input common mode voltage. Temperature drift on the Vocm offset voltage will show up directly as output Vocm drift. Temperature drift on the Vos and Ios terms will have the same gain as the static values, the NG for Vos and Rf for Ios.
The input stage CMRR is usually high enough to be a minor error contribution in these precision FDAs. The simple test of Figure 5 drives a +/-2V input to matched 1k Ω Rf=Rg resistors. This will divide down to a +/-1V input Common Mode (CM) swing which produces the very small 3.56μV input error voltage due to CMRR. This error swing calculates out to 115dB CMRR matching the plot (Figure 41, ref. 14) but not the typical 110dB CMRR specification. This small positive +μV/Vcm effect then gets to the output times the NG.