Probably no single issue faces more high-speed signal path designers (and supplier support teams) than the risk of instability in higher speed op amps and fully differential amplifiers (FDA). Some legacy literature assumes approximations that might not be prudent. Background on how to think about signal path stability issues will be first reviewed. Some detailed improvements in stability simulation approaches will then be presented. More detailed caveats on the 40dB closure rate warnings will then be developed using the transimpedance application circuit as an illustration vehicle. This will be followed up with Voltage Feedback Amplifiers (VFA), Current Feedback Amplifiers (CFA) and FDA stability hazards “and fixes” in subsequent insights.
Common Sources of Instability in High Speed Signal Channel Solutions
By far the most common instability issue, arising from low phase margin, is the overall loop gain for these negative feedback amplifiers. There are other, less common sources that should be considered in special cases – such as:
- Cascaded high gain amplifier stages oscillating through a power supply feedback loop.
- Emitter follower input stage local oscillation through an inductive source impedance – e.g. trace inductance looking out to a grounded input.
- Internal bias lines finding instability through external capacitive de-coupling with low self-resonant frequencies – arising from poor cap placement with higher trace inductance.
- Differential I/O stages showing a common mode loop instability (section 8.1.5, ref. 1)
These special cases will not be considered here, but some appear in earlier application notes. (ref. 2).
Finding a sustained or intermittent oscillation in EMC, or at final board testing, is the wrong place to discover an issue. Actually, finding a sustained oscillation in a signal path design is relatively trivial. Finding a “potential” for instability is far more difficult, but the right place and time to apply the effort – and is the topic for this discussion. These always come down to assessing the “nominal” stage Phase Margin (PM) and then judging the chance of moving down in production and over temperature to an unstable condition. Numerous earlier publications of Loop Gain (LG) analysis establish the framework for this discussion (ref. 3,4,5). There are slight variations in these sources, but they are fundamentally looking for the difference between a -180deg phase shift around the loop at the frequency the LG magnitude drops to “1” (or 0dB) will give the “phase margin” (PM). It is rare that an op amp or Fully Differential Amplifier (FDA) application will have good phase margin, but poor “Gain Margin”; we will focus on phase margin here. Some sources simply reverse the polarity of the LG sense to produce a +180 degree at DC. This then shows PM directly as it transitions towards 0 degrees.
Various “rules of thumb” have emerged over time. Those really need to be in the context of the application circuit and what opportunities are available for variation in the direction of reduced phase margin from nominal. Legacy VFA op amp data sheets often would target a nominal 45 degree PM at the lowest gain to get a higher reported small signal bandwidth (especially for National Semiconductor) along with the nominal 2.3dB small signal response peaking that comes with 45 degree PM. In more recent device applications, much lower PMs are sometimes allowed. However, while one source might claim a “minimum 30 degree phase margin” to be perfectly suitable and safe in the context of a particular source of lower nominal phase margin, some other more aggressive targets like a minimum 20 degree nominal PM might be perfectly acceptable when the terms creating that nominal have minimal variation in production or over temperature – and, the effects of that low nominal phase margin are acceptable in the context of the intended application.
Generally, phase margins <55 degrees will start to show more ringing and longer settling times if the application is pulse-response oriented. Really low nominal phase margins, in these time domain-oriented channels, are normally not acceptable unless post filtering places these resonances far into the cutoff band. Similarly, phase margins <55 degrees will start to show response peaking in frequency domain-oriented applications. This is sometimes a secondary effect to an intentional effort to increase the loop gain (improving distortion) at lower frequencies where that peaking at higher frequencies will either be cut off by passive postfilters or can be ignored since that peaking is above the signal “band” of interest. However, if it shifts in production or over temperature into oscillation, it can rarely be ignored!
One important reference point in closed loop amplifier phase margins is that a Θm = 65.5 degrees will give a closed loop Butterworth response. Ideally, that 2nd order shape will have no response peaking in the passband but will give a 4.3% step response overshoot. More generally, the ideal mapping from phase margin to response Q, dB peaking, and step response overshoot are shown in Figures 1→3. These are small signal effects where encroaching into an output slew limited response will depart widely from these relationships (ref. 6, 7).
Closed loop response Q vs. LG phase margin.
Small Signal (non-slew limited) response peaking vs. LG phase margin.
Small Signal (non-slew limited) Step Response Overshoot vs LG phase margin.
One of the more confusing (and rarely discussed) aspects to LG analysis at a particular LG=0dB (Fxover) crossover frequency and Phase Margin (PM), what then will be the closed loop Small Signal BandWidth (SSBW)? The commonly reported Gain Bandwidth Product (GBP) idea only applies if the PM=90 degrees (a single pole system). A good approximation to the F-3dB/ Fxover ratio shown in Figure 4 applies to a 2-pole system. Higher order LG situations depart from this again, but this gets one step closer to explaining the measured SSBW vs gain in VFA devices. This curve goes flat at 1.57X for PM < 35 degrees. Going back to the nominally Butterworth shape with Θm = 65.5 degrees will predict an F-3dB = 1.55*Fxover – far higher than the simple GBP concept would predict.
SSBW extension from LG=0dB Fxover vs Phase Margin at Crossover.
An op amp or FDA will get into a lower phase margin condition due to added poles around the loop (kind of by definition). These most commonly arise from capacitive loads interacting with the open loop output impedance or capacitance on the device feedback node(s) introducing a feedback pole in conjunction with the feedback impedance. More recently, devices with lower nominal phase margin, and highly reactive open loop output impedance characteristics, increase the risk of low nominal phase margin. Sometimes, the intended application circuit can also create a low phase margin condition that will require attention. But first, what methods can be used to estimate nominal phase margin in simulation?