Simulation Approaches to Estimating Nominal Phase Margin.
A signal path that is already oscillating has one set of tools to locate the suspect loop. But once isolated, and for the wider range of circuits with low (but not oscillating) phase margins, it is normally necessary to then go into simulation to prove paths to increase the phase margin if needed. At that point, the accuracy and feature set in the vendor models become paramount. These models have improved over time where the key elements required to have some hope of efficacious Loop Gain (LG) phase margin estimates include:
- Parasitic input impedance (normally a common mode and differential mode RC network)
- Open loop gain and phase from the error signal to the output voltage – sometimes this should be no load initially as the open loop output impedance will be added separately. The dominant open loop pole setting the GBP is critical, but no more so than the correct gain and phase near Aol = 0dB.
- Open loop output impedance (Zol) over frequency. This has received a lot of attention lately (ref.8), and is indeed critical to accurate PM estimates. It seems many of the older amplifier models (device library, ref. 9) have a very simplified resistive only Zol model that might not be enough for accurate PM estimates in more complicated load and/or feedback network conditions using higher frequency devices.
There are certainly multiple approaches to arrive at an op amp or Fully Differential Amplifier (FDA) LG simulation. The most thorough approaches apply a 2-pass simulation with either the loop broken (Rosenstark’s, ref. 10) or with two inside-the-loop simulations (Middlebrook’s, ref. 11). A recent discussion compares these two (ref. 12). Those approaches all note that if the signal injection point is widely different in impedance looking each direction, a single simulation will be enough. This is the approach most application teams take where then there is some disparity in where the loop is broken. There are some concerns that breaking the loop for simulation gets into DC operating point issues – those can be easily handled as shown here. Some legacy material using this approach had simplifying assumptions that might not be as effective using modern higher speed device models (ref. 13). Both this older approach, and a slight modification that will improve the accuracy, will be shown using a very recent device model for the OPA837 (ref. 14).
It is very typical for suppliers to illustrate a LG phase margin simulation with fairly benign external circuit conditions. It is not uncommon for end systems to immediately depart from those towards lower phase margin designs in the course of setting up the desired signal path characteristics. A fairly straightforward closed loop design using the OPA837 is shown in Figure 5. Here, an initial gain of -1V/V is bandlimited at 796kHz using a simple 100pF feedback capacitor. Combined with even a modest capacitive load (like a scope probe), this will immediately produce a low phase margin design – primarily due to the very reactive open loop output impedance (shown in Figure 6) for the OPA837. Setting that feedback Cf to 0pF shows the wideband result with minimal peaking in Figure 5.
The noise gain (NG) in this circuit starts at 6dB (NG of 2V/V) at DC, then transitions to 0dB as the feedback capacitor shorts out. The resonance with Cf = 100pF at 66MHz arises from the open loop output impedance interacting with the feedback Cf. To extract the open loop output impedance (Zol) within the OPA837 model, use the technique of very high L and C in Figure 6 to setup the DC operating point. For the AC simulation, that L opens up and the C shorts out leaving an open loop model sitting at a mid-supply DC operating voltage. The odd LC values reduce numeric chatter while the small series R with the feedback L helps find a DC operating point in some cases. The complicated Zol shape of Figure 6 has started to show up in rail-to-rail output (RRO) devices but has only recently been captured in the vendor models. Many older models have a simple fixed resistive Zol. That might be correct for higher quiescent current bipolar non-RRO output designs but might not be for RRO type devices. Use the approach of Figure 6 to evaluate the model for Zol in the device you are using.
To test if this effect is dominant, modify the schematic of Figure 5 to isolate the Zol from the load and feedback network using a dependent source. Doing this removes the resonance effect in Figure 7.
Simply adding a bandlimiting capacitor in the feedback path has pushed this design into an obviously low phase margin condition. The next step would be to set up for a phase margin simulation to assess where we are before moving on to testing improvement techniques. An older technique will be shown first with a slight improvement to follow.
One approach commonly shown (ref. 15) breaks the loop going into the feedback network then injects a signal back into the feedback path and sensing the Loop Gain (LG) back around to the output of the op amp. Figure 8 shows this approach where it is estimating a 30 degree phase margin for the example of Figure 5. The polarity of VM1 is showing the phase shift around the loop. Starting at -90 degree from the op amps’ dominant pole at lower frequencies it shifts down to -150 degrees at the LG=0dB xover point. That is then subtracted from -180 degrees to get that 30 degree phase margin. Reversing this sense voltmeter polarity would add 180 degrees to what is plotted allowing the “phase margin” to be read off directly.
This approach captures most of what we are after and is very often adequate to the task. The models’ Zol correctly sees the load and the feedback network correctly sees the inverting input parasitic capacitance in the model before it gets into the Aol response of the op amp. However, this legacy approach isolates the feedback impedance from the Zol. Often, that is not an issue if the feedback network is purely resistive and/or the Zol is a simple low R model. In the more general case, the setup of Figure 9 is slightly more accurate. Here, the loop is broken at the input where the output Zol is connected to both the load and feedback network.
The only new requirement is to manually place RC elements for the inverting input impedance at the summing junction where the LG measurement is made. This more accurate approach shows a very low 20.3 degree phase margin where here the VM1 polarity has been reversed to allow “phase margin” to be read off directly. The lower phase margin vs. Figure 8 is a direct result of the open loop Zol seeing the added reactive loading of the feedback network. Reducing Cf to 0pF in this test simulation increases the phase margin to 52 degrees. Figure 2 predicts a 1.22dB peaking for that phase margin, closely matching the 1.37dB peaking in the Cf=0pF curve of Figure 5.
It would seem this setup #2 might be the more accurate approach. And, going back to the two pass approaches, the input break point would seem to give a wider divergence in impedance looking the two directions at the break. This approach will be used in subsequent insights to show paths to improve PM, but first: