While there has been a vast record of earlier work (ref. 1) on this topic, here we will combine a few concepts to show some emerging issues and paths to improve the Phase Margin (PM) for VFA stages that have slipped into perhaps an unsuitably low margin condition. Starting with the most ubiquitous issue of load capacitance induced problems, we will move on to how to improve that and correctly assess if indeed you are going in the right direction. What will emerge is perhaps a combination of approaches should sometimes be considered. Some of this will apply to CFAs and FDAs as well, but those also have their own special issues considered in upcoming insights.
What is the Deal with Load Capacitance Induced Phase Margin Loss?
Most op amps and FDAs (with one exception, in insight #7) will, to varying degrees, be adversely affected by parasitic or intentional load capacitance. The literature approaches this effect from a number of directions the best I have found is to think of it in terms of what that Cload is doing with a simple open loop output resistance (Rol) to the overall Loop Gain (LG) phase. This simple approach breaks down again with more reactive open loop Zol (Figure 6, ref. 2), but is valuable for its intuitive insight.
An unloaded VFA op amp (the 2kΩ Rload is a typical sense path load) starts out with some Loop Gain (LG) Phase Margin (PM) that can then get degraded by adding a capacitive load. Figure 1 shows this example using a relatively simple OPA725 TINA model (ref. 3) with 2 real poles in the Aol response and resistive open loop output Rol. This gain of +2V/V case using 2kΩ values is already showing what looks like a lower phase margin than a simple 90o. This is using the TINA simulator tool (ref. 4).
The input capacitance in the model (9pF) is interacting with the Rf||Rg driving impedance in the feedback network to introduce a feedback pole at 1/(2π*1kΩ*9pF) = 17.7MHz. The LG phase margin extract in Figure 2 (ref. 2) shows a LG=0dB crossover at 9.46MHz with 56o phase margin.
The 1.1dB closed loop peaking in Figure 1 agrees with the expected peaking for 56o phase margin (Figure 2, ref. 2) while the 17.1MHz F-3dB is reasonably close to the expected 1.6*Fcrossover = 15.1MHz (Figure 4, ref. 2).
This simple design is already starting with a bit lower 56o phase margin before any Cload is added which will only move the phase margin down due to the pole that will be introduced by the 112Ω open loop output impedance in this model (Figure 6, ref. 2 for setup). Adding a 100pF load does indeed raise the peaking to 6dB suggesting a phase margin near 30o (Figure 2, ref. 2). Adding a 100pF load to the Figure 2 LG simulation shows 31o phase margin.
One way to see what is happening is to set up a simulation for the signal from the output stage to the inverting node and look at the response right at the output pin as shown in Figure 4. This is the β in the LG where that direct 100pF capacitive load has introduced a pole in the β at 15MHz which becomes a zero in the Noise Gain (NG) response. The phase of that zero in the NG ( a positive number now) is subtracted from the op amp Aol to get the LG phase. Or, equivalently, the β phase is added to the Aol phase shift.
The most common fix for phase margin loss due to capacitive loads (ref. 1d) is to add a series Riso before that Cload. This acts to change the simple pole at the output pin to a pole/zero pair pulling the phase shift back up at the output pin before the feedback signal heads back the inverting node. Since this example starts out with only 56o phase margin, adding an Riso cannot improve the phase margin beyond that. However, targeting an improvement from 31o to 45o adding an Riso before the 100pF in the LG simulation of Figure 2 shows 120Ω would be required. Starting out with an unloaded PM > 65o would allow much lower Riso values to be used as capacitive loads are added (Figure 16 below). Adding an Riso to the circuit in Figure 5 shows we have added a zero to the β phase response it is this pulling up of the phase that makes this approach effective.
Putting Riso = 120Ω into the closed loop gain of +2V/V OPA725 circuit of Figure 6 certainly reduced the peaking where the 2.7dB peaking over the 6dB DC gain at the output pin approximately agrees with a 45o phase margin peaking (Figure 2, ref. 2). The response at Cload is now attenuated to 5.52dB DC gain by the 120Ω Riso where that simple RC reduces the peaking at the Cload to 1.6dB.
Changing a simple pole at the output pin by adding an Riso into a pole/zero pair can also be done effectively by adding the R in series to ground with the Cload (and out of the output pin line) when that is an option. This is often seen in SAR reference line buffer designs such as Figure 7. (Figure 10, ref. 5). Here, a composite amplifier circuit using the OPA837 (ref. 6) as the output stage drives directly into the 10μF load capacitors. This OPA837 circuit also improves the capacitive load phase margin using the dual loop approach (Figure 32, ref. 7) but then adds 0.2Ω in series with each of the load caps to ground as well. Testing just this OPA837 output stage for phase margin showed 49o.
When the load capacitance is known, and cannot endure the effects of an outside the loop Riso, the dual loop approach can be used. This technique to directly driving a capacitive load closes the loop at DC with the outer resistive loop to get gain accuracy to the capacitive load. The inner loop effectively shorts out the outer loop as the frequency increases putting the op amp in a unity NG condition with the Rx inside the loop isolating the Cload from the op amps open loop output impedance.
There are several descriptions of this design (ref.1c,e,f), but the simplest approach is shown in Equation 1 and 2 (from Figure 32, ref. 7). Here, a desired closed loop Butterworth F-3dB is selected to be well below the op amp Gain Bandwidth Product (GBP) and the inside the loop Rx and feedback capacitor Cf solved as shown.
Figure 8 shows an example using the OPA725 driving a 1nF load and targeting a 2.5MHz F-3dB. Running non-inverting gain of +2V/V this is approximate with its 1dB peaking and 3.1MHz F-3dB due to the 9pF parasitic input C on the inverting input. Placing a 9pF compensating capacitor across the feedback resistor flattens this response (Figure 16). Figure 8 also shows the op amp output pin is peaking even more -but the simple 1/(2πRxCload) pole rolls this off a bit. Using this approach, you should check your step response at the op amp output pin to confirm clipping is not occurring. If this slight peaking is not acceptable, simply increase Cf until the desired response shape is achieved and/or add a compensating capacitor across Rf (Figure 16).