Emerging Capacitive Load Drive Issues with Newer Parts and Updated Resolutions
and dual loop approaches have been pretty standard where the latter only applies to unity gain stable VFA. So what options are available when you need to drive a capacitive load using a decompensated op amp like the recent OPA838 (ref. 8)? First, a hidden risk inside the typical Riso
plots shown in Figure 9 (ref. 8) where the circled curve should give cause for caution. The total measured response is always a combination of whatever peaking is happening at the output pin rolled off by the 1/(2πRiso
) pole. The circled curve is showing an RC rolloff at 12.2MHz that is then getting overridden by what might be significant peaking at the output pin.
The fact there are different Riso curves parametric on gain in Figure 9 is another way of saying what you need to improve the phase margin depends a lot on where you are starting from. Hence, higher gain settings start out with more phase margin and will show lower required Riso for the same Cload. However, zooming in on that gain of +6V/V 100pF load curve suggesting an Riso = 130Ω, shows there is perhaps more output pin peaking than desired in Figure 10.
This is another instance where the peaking at the op amp output pin is much higher than the RC rolled off version measured at the Cload. Figure 11 shows the LG simulation for this where the 28o phase margin corresponds to the 6.2dB peaking in Figure 10. (Figure 2, ref. 2). The LG meter is rotated in Figure 11 to report phase margin directly. This 28o phase margin closely matches the reported 30o target in Figure 8.
This circuit is peaking at the op amp output 6dB at about 39MHz where the simple 1/(2πRisoCload) pole is rolling that off at 12MHz. Beware this hazard for faster parts showing a higher recommended Riso than you might expect. It is always best to run a LG phase margin test confirm adequate margin and not depend only on the final Cload response.
Shaping the Noise Gain to Higher Initial Phase Margin
Many of the older references note that operating with higher noise gain (before the Cload is added) can improve the initial phase margin and allow lower Riso. Those suggestions are normally fixed resistors or RC networks across the inputs – both increase the broadband noise. If the design can operate inverting, an older inverting compensation technique can be applied here to shape the noise gain up over frequency. This has the benefit of retaining the lower frequency loop gain, lower noise, and the higher slew rate of a decompensated device while shaping to a higher noise gain only at higher frequencies. This inverting compensation (recently rebuilt from the August 1997 original and reposted on EDN, ref. 9) can be used to shape to a higher phase margin with no load to allow lower Riso values when a capacitive load is added. Let’s set up some targets for the OPA838 and see what this will take.
- Gain = -5V/V with Rg = 400Ω, Rf = 2kΩ, Low frequency NG1 = 6 (min. specified gain)
- High frequency noise gain target NG2 = 24V/V --(1+Cs/Cf) sets this.
- Cload = 100pF
- Riso = ??
Using the design equations below (page 12, ref. 10), and the 300MHz GBP for the 1mA OPA838 (ref. 8) , first find the Zo frequency for this nominally 2nd order Butterworth response solution – Zo is where the projection of the rising portion of the noise gain going down in frequency intersects 0dB in the Bode LG plot (ref. 9).
Zo = 357kHz
Now solve for the required capacitor across the 2kΩ feedback resistor. This is a case where the reactive open loop output impedance in the OPA838 model will interact with this feedback Cf to yield results slightly mismatching the 2nd order phase margin to Q estimates (ref. 2) as this becomes a >2nd order situation.
Cf = 9.3pF
And then to hit the higher frequency noise gain of 24V/V, add a capacitor on the inverting node to ground:
Cs = 214pF where the approximate closed loop bandwidth (before Cload is added ) will be:
F-3dB ≈ 10.4MHz where the actual increase in the noise gain due to the noise gain zero starts at (ref. 9).
NG1*Zo = 2.14MHz.
This inverting circuit, with the compensation capacitors, is shown in Figure 12 where the resulting shape looks very close to the expected Butterworth with 11.3MHz F-3dB. Without these NG shaping caps, the closed loop response is peaking approximately 3.3dB with much higher bandwidth. The NG shaping caps are improving the phase margin at the cost of lower closed loop bandwidth.
Now, before we add a Cload and find the right Riso, run a LG simulation in Figure 13 where the Butterworth would be near 65o phase margin. The actual results show 58o phase margin due to the reactive Zol interacting with Cf – but a better place to start as the capacitive load is added and Riso resolved than the 39o implicit in the 3.3dBp peaked curve in Figure 12.
Going back to the closed loop circuit and adding the Cload allows a much lower (than Figure 10) Riso = 70Ω to be found that shows a more well controlled response shape at both the output pin and Cload points. Figure 14 shows the bandwidth has extended out to 18.8MHz in what is clearly more than a 2nd order response shape due to the peaking Zol in the OPA838 model.
This shaped noise gain approach appears to give an excellent response shape with the 100pF capacitive load and Riso = 70Ω. This is essentially moving the core op amp into a better phase margin place before the Riso and Cload are added and could also be applied to unity gain stable op amps if needed. It is peaking the noise gain over frequency, so check the spot noise at the output pin and capacitive load. Figure 15 shows the added simple 1/(2πRisoCload) pole at 23MHz is rolling off the more peaked spot noise at the op amp output pin that starts rising at the noise gain zero of 2.1MHz.