The Current Feedback Amplifier (CFA) burst onto the scene in the mid-1980s with the commercialization of this new topology by Comlinear Corporation. It quickly propagated industrywide with many variants and feature sets. Over time, it settled into being the dominate solution for video line driving, wireline communications (xDSL, G.Hn, Powerline comms, etc), and AWG output stages. While it certainly has the same capacitive load stability issues as the high speed VFA device, the details are necessarily different given the current feedback architecture. Here, an updated Loop Gain (LG) simulation approach will be first detailed and then used to show paths into, and out of, low Phase Margin (PM) conditions.

Much like the VFA LG setup of Reference 1, we need to break the loop at the input and re-introduce the inverting node parasitic impedance to get a valid LG simulation. Here, the AC stimulus into the open loop amplifier model will be a current into the inverting node where the measurement around the loop will be the feedback current that splits off at the inverting node into the input impedance in parallel with the R_{g} element. Vendor simulation models vary greatly in the accuracy and feature set where some of the earlier (full transistor level) models are the best. More recent lumped element macromodels (Reference 2) can also do very well if enough attention is paid to inverting input impedance, open loop transimpedance gain Z(s), and open loop output impedance elements. While the VFA input impedance is usually in the datasheet, the CFA will often have an open loop resistance looking into the inverting input often modelled as only a resistor. This is normally adequate but, strictly speaking, there is always an inductive element in series as well.

The open loop impedance looking into a CFA inverting input (this is the output of the unity gain buffer across the inputs, Reference 3) will always be at least a series R plus an inductance in some cases. Those buffers are normally open loop with complementary emitter followers looking into the inverting node that will have an inductive characteristic at very high frequencies (>1GHz). Some unique devices, like the OPA684 and OPA683 (References 4,5), have a closed loop buffer to reduce the DC impedance looking into the inverting input. This is great for achieving a wider range of “Gain Bandwidth Independence”, but will now have a much higher equivalent inductance as the buffer loop gain rolls off. This gives a unique closed loop response shape vs. closed loop gain as shown in Figure 1 (Reference 4, front page). Here, the feedback resistor is fixed at 1kΩ and only the R_{g} element is varied to illustrate the relatively wide range of high bandwidth over gain that this closed loop input buffer can provide. The +3dB peaking at gain of 50V/V is unusual, but is due to the higher equivalent input inductance caused by the closed loop input buffer’s own LG rolloff.

**Figure 1**

**Closed loop response vs. Gain for the OPA684**

Figure 2 shows a simulation to extract that inverting input open loop impedance for the OPA684 TINA (Reference 6) model (Reference 7). Looking at the low frequency input impedance (in dBohms), and then the +3dB point from that, gives an impedance model looking into the open loop inverting input as:

- Rin = 4.3ohms
- L = 73nH

**Figure 2**

With this inverting input impedance model extracted, we can now go on to set up for an overall LG simulation to test the phase margin as shown in Figure 3. This is similar to the VFA LG simulation (Reference 1) in that the loop is broken at the input with the DC operating point set by the large feedback inductor with (in this case) a test current injected through the large capacitor into the inverting input and the total loop gain traced back around to the portion of the feedback current that splits off from R_{g} into the open loop inverting input impedance model. Here again, the specified load for the closed loop measurement (100Ω here) is in place to include any open loop output impedance effects in the model (note, this simulation was suffering significant numerical chatter until it was changed to a Davis KLU matrix matrix solver under the “Analysis” options in TINA)

**Figure 3**

The polarity of the feedback current sensing element plots phase margin directly and shows 43^{o} at a LG=0dB frequency of 43MHz for this gain of 50V/V test. That 43^{o} phase margin maps to a closed loop 3dB peaking (Figure 2, Reference 8) while the 1.6X multiplier from LG=0dB crossover to F_{-3dB} (Figure 4, Reference 8) matches the 70MHz F_{-3dB} at a gain of 50V/V in Figure 1.

While it is certainly gratifying to (finally) explain that +3dB peaking in the OPA684 gain of 50V/V using this LG simulation mapping to closed loop (with Figure 2,4 in Reference 8), this is probably too special a case for the much wider range of CFAs with open loop input stage buffers operating at higher quiescent current. To continue with more typical CFA designs, use the OPA691 (Reference 9) as a more representative device and model. Repeating the inverting input impedance extraction of Figure 2 for the OPA691 shows a 47Ω inverting input resistance. The normal approach (Reference 3) to holding closed loop bandwidth relatively constant over gain is to adjust the R_{f} value down with increasing gain (Figure 8, Reference 9). Repeating Figure 3 for the OPA691 at a gain of 2V/V will give Figure 4 showing 58^{o} phase margin with a LG=0dB at 142MHz.

**Figure 4**

This agrees with the minimal peaking in the measured small signal response shown in Figure 5 (page 5, Reference 9). The measured 230MHz F-3dB closely agrees with the estimated 1.6XF_{xover} = 227MHz (Figure 4, Reference 8).

**Figure 5**

**Measured small signal response over gain for the current feedback OPA691. **

Now going to the recommended gain of +5V/V condition with Rf =261, the LG=0dB phase margin shows a very similar result to the gain of +2V/V LG simulation of Figure 4 explaining the close match between the gain of +2V/V and +5V/V curves in Figure 5.

**Figure 6**

This simple approach to holding a fixed closed loop response vs. gain is based on the LG expression (Reference 3) given in Equation 1 where Z(s) is the open loop frequency dependent transimpedance gain from the inverting input current to the output voltage of the op amp for a given load and R_{in} is the open loop inverting input resistance.

Holding the feedback transimpedance (denominator in Equation 1) constant over gain is simply solving the optimum value (for about 60^{o} phase margin) by solving Equation 2 for the required Rf as the signal gain changes. Equation 2 is showing the gain of 2V/V solution for the OPA691. Solving this for a gain of +5V/V suggests an R_{f} = 261Ω as shown in Figure 5.

This approach to constant closed loop bandwidth will eventually breakdown as the R_{g} value gets so low as to bandlimit the unity gain buffer across the inputs. Figure 7 shows a closed loop response probing the inverting pin (buffer output response) and the output for a gain of 10V/V using the OPA691 and the recommended R_{f} of Figure 5. The minimum R_{g} is usually limited to 20Ω due to this effect. Here, the buffer F_{-3dB} at 152MHz is actually being extended by the overall loop gain to a 191MHz output F_{-3dB}.

**Figure 7**

Normally, the buffer SSBW is >10X the overall closed loop bandwidth with higher R_{g} values. Repeating Figure 7 for a gain of 2 with R_{f} = R_{g} = 402Ω gives a buffer F_{-3dB} of 4GHz.