The popular FDA comes in both Current Feedback Amplifier (CFA) and Voltage Feedback Amplifier (VFA) variants. The CFA versions tend to be used in AC-coupled applications where their great full power bandwidth can be used to advantage while their poor DC precision will have no impact. The VFA versions emerged first (Reference 1) and have by far the largest representation in these product families. Early developments crossed many process nodes to deliver a range of higher voltage, slower, devices then on into >1GHz 5V supply versions (Reference 2). The most recent VFA FDAs focus on lower power, precision, solutions more aimed at Successive Approximation Register (SAR) and delta sigma ADC support. Those will be focus in this FDA stability discussion - but the concepts are backward compatible to the earliest VFA FDAs.
Setting up for a Current Feedback FDA Loop Gain (LG) simulation.
Similar to the CFA op amp LG simulation approach (Reference 3), the key is to break the loop at the input, inject a test current signal, then trace the loop through the amplifier’s internal forward “transimpedance” path and then back into the differential low impedance inputs as a “current feedback” while placing their differential input impedance in the sense path. The feedback is always differential, but the application circuit could have either single ended or differential inputs. A single ended stimulus will bring the internal common mode loop dynamics into play. Since those bring in another level of modeling accuracy, and the models appear uneven in their treatment of this loop. A simpler differential input condition will be the focus here using balanced supplies and a centered common mode control at ground. While there are relatively few CFA based FDAs, these do bring an unmatched level of slew rate to the available FDA universe as shown in Table 1.
Select the fastest LMH6554 (Reference 4) for simulation testing where its model is transistor-based as opposed to a lumped-element macromodel. First, the open loop differential input impedance is required and can be extracted using the setup of Figure 1.
This dBohm plot is showing a low frequency differential input impedance of 48Ω with a -3dB frequency indicating a 1.8pF in parallel. (Note: this simulation showed a lot of numerical chatter that was resolved by switching to a Davis KLU matrix solver under the Analysis “options” in TINA (Reference 5), the summing junction input pins are labelled backwards in the current TINA symbol for the LMH6554).
Moving on to a Loop Gain (LG) phase margin simulation, break the loop at the input pins, injecting a differential input current, then measure the resulting differential input error current through that input impedance model as shown in Figure 2. Here, the input error current sense ammeter reads phase shift around the loop where a -128o at the 1.7GHz LG=0dB crossover indicates 52o phase margin.
Using the 1.6X F-3dB bandwidth multiplier (Figure 4, Reference 6) from this 1.7GHz Fxover predicts a 2.7GHz Small Signal BandWidth (SSBW) – closely matching the reported 2.8GHz (Reference 4).
Tuning in the capacitance load driver solution using the LMH6554
Similar to the CFA op amp case (Reference 3), the current feedback FDA will have an open loop output impedance that will introduce an added pole in the loop if a capacitive load is added to the output. Normally, that capacitance will be either a layout parasitic, part of a post filter, or an ADC input load. Using a similar approach (Reference 3) to simulating the open loop differential output impedance showed a remarkably low 1.9Ω. This certainly begs the question if that is correct and, if so, suggests a closed loop output stage. If accurate, this small Zol will have little impact on the loop phase margin as cap loads are added. Just like the CFA op amp capacitive load case, the response to the cap load is combination of whatever might be happening across the output pins then rolled off by the RC filter to the load. The recommended curves from the LMH6554 datasheet (Figure 3) show what appear to be relatively high Ros (or ROUTs) for such low open loop output impedance. This may be a consideration for a secondary effect (like local oscillations in a closed loop output stage), but at this point can only depend on the model accuracy and proceed.
These are at a gain of 1 with 200Ω resistors where the responses to the output pins and load are shown using the TINA simulation model in Figure 4 for the 18pF case. The lack of peaking at the output pin suggests quite a lot of phase margin with this initial setting. The higher than necessary Ro also gives the relatively low 286MHz F-3dB to the load vs the 1.1GHz across the output pins. It does appear this loading has dropped the simple 200Ω load SSBW of 2.8GHz quite a lot.
Repeating the Figure 2 Loop Gain (LG) test with this new load gives the 52o phase margin of Figure 5. Also, this crossover frequency far exceeds the closed loop bandwidth indicating some other factor is coming in to bandlimit the closed loop result. The open loop output impedance also showed an inductive characteristic above 1GHz and it is likely this is contributing to the bandlimiting.
At least at the model level, this seems excessively conservative and lower Ro values should be possible extending the bandwidth to the Cload over what appears in Figure 4. It proved actually difficult to force peaking at the output pins with value changes. Reducing both the Ro and the feedback/gain resistors should both be moving in the direction of lower phase margin and bandwidth extension at the load. Figure 6 shows an example with only 3Ω Ro and the Rs reduced to 150Ω where 43o loop phase margin results.
Reducing the amplifier Rs will also reduce the noise while the lower Ro will greatly extend the SSBW to the capacitive load as shown in the closed loop simulation in Figure 7.
Still no peaking at the output pins but the SSBW to the cap load is vastly extended to 850MHz from the datasheet condition of 286MHz. To the extent this model is accurate, this approach can offer considerably more frequency range than Figure 3 suggests. The same ideas presented in Reference 3 can be applied here to adapt what are normally VFA only application circuits to CFA-based FDAs.