The popular FDA comes in both Current Feedback Amplifier (CFA) and Voltage Feedback Amplifier (VFA) variants. The CFA versions tend to be used in AC-coupled applications where their great full power bandwidth can be used to advantage while their poor DC precision will have no impact. The VFA versions emerged first (Reference 1) and have by far the largest representation in these product families. Early developments crossed many process nodes to deliver a range of higher voltage, slower, devices then on into >1GHz 5V supply versions (Reference 2). The most recent VFA FDAs focus on lower power, precision, solutions more aimed at Successive Approximation Register (SAR) and delta sigma ADC support. Those will be focus in this FDA stability discussion - but the concepts are backward compatible to the earliest VFA FDAs.
Setting up for a Current Feedback FDA Loop Gain (LG) simulation.
Similar to the CFA op amp LG simulation approach (Reference 3), the key is to break the loop at the input, inject a test current signal, then trace the loop through the amplifier’s internal forward “transimpedance” path and then back into the differential low impedance inputs as a “current feedback” while placing their differential input impedance in the sense path. The feedback is always differential, but the application circuit could have either single ended or differential inputs. A single ended stimulus will bring the internal common mode loop dynamics into play. Since those bring in another level of modeling accuracy, and the models appear uneven in their treatment of this loop. A simpler differential input condition will be the focus here using balanced supplies and a centered common mode control at ground. While there are relatively few CFA based FDAs, these do bring an unmatched level of slew rate to the available FDA universe as shown in Table 1.
Select the fastest LMH6554 (Reference 4) for simulation testing where its model is transistor-based as opposed to a lumped-element macromodel. First, the open loop differential input impedance is required and can be extracted using the setup of Figure 1.
This dBohm plot is showing a low frequency differential input impedance of 48Ω with a -3dB frequency indicating a 1.8pF in parallel. (Note: this simulation showed a lot of numerical chatter that was resolved by switching to a Davis KLU matrix solver under the Analysis “options” in TINA (Reference 5), the summing junction input pins are labelled backwards in the current TINA symbol for the LMH6554).
Moving on to a Loop Gain (LG) phase margin simulation, break the loop at the input pins, injecting a differential input current, then measure the resulting differential input error current through that input impedance model as shown in Figure 2. Here, the input error current sense ammeter reads phase shift around the loop where a -128o at the 1.7GHz LG=0dB crossover indicates 52o phase margin.
Using the 1.6X F-3dB bandwidth multiplier (Figure 4, Reference 6) from this 1.7GHz Fxover predicts a 2.7GHz Small Signal BandWidth (SSBW) – closely matching the reported 2.8GHz (Reference 4).
Tuning in the capacitance load driver solution using the LMH6554
Similar to the CFA op amp case (Reference 3), the current feedback FDA will have an open loop output impedance that will introduce an added pole in the loop if a capacitive load is added to the output. Normally, that capacitance will be either a layout parasitic, part of a post filter, or an ADC input load. Using a similar approach (Reference 3) to simulating the open loop differential output impedance showed a remarkably low 1.9Ω. This certainly begs the question if that is correct and, if so, suggests a closed loop output stage. If accurate, this small Zol will have little impact on the loop phase margin as cap loads are added. Just like the CFA op amp capacitive load case, the response to the cap load is combination of whatever might be happening across the output pins then rolled off by the RC filter to the load. The recommended curves from the LMH6554 datasheet (Figure 3) show what appear to be relatively high Ros (or ROUTs) for such low open loop output impedance. This may be a consideration for a secondary effect (like local oscillations in a closed loop output stage), but at this point can only depend on the model accuracy and proceed.
These are at a gain of 1 with 200Ω resistors where the responses to the output pins and load are shown using the TINA simulation model in Figure 4 for the 18pF case. The lack of peaking at the output pin suggests quite a lot of phase margin with this initial setting. The higher than necessary Ro also gives the relatively low 286MHz F-3dB to the load vs the 1.1GHz across the output pins. It does appear this loading has dropped the simple 200Ω load SSBW of 2.8GHz quite a lot.
Repeating the Figure 2 Loop Gain (LG) test with this new load gives the 52o phase margin of Figure 5. Also, this crossover frequency far exceeds the closed loop bandwidth indicating some other factor is coming in to bandlimit the closed loop result. The open loop output impedance also showed an inductive characteristic above 1GHz and it is likely this is contributing to the bandlimiting.
At least at the model level, this seems excessively conservative and lower Ro values should be possible extending the bandwidth to the Cload over what appears in Figure 4. It proved actually difficult to force peaking at the output pins with value changes. Reducing both the Ro and the feedback/gain resistors should both be moving in the direction of lower phase margin and bandwidth extension at the load. Figure 6 shows an example with only 3Ω Ro and the Rs reduced to 150Ω where 43o loop phase margin results.
Reducing the amplifier Rs will also reduce the noise while the lower Ro will greatly extend the SSBW to the capacitive load as shown in the closed loop simulation in Figure 7.
Still no peaking at the output pins but the SSBW to the cap load is vastly extended to 850MHz from the datasheet condition of 286MHz. To the extent this model is accurate, this approach can offer considerably more frequency range than Figure 3 suggests. The same ideas presented in Reference 3 can be applied here to adapt what are normally VFA only application circuits to CFA-based FDAs.
New phase margin issues using RRout high speed VFA FDAs.
New phase margin issues using RRout high speed VFA FDAs.
Starting from a wide range of very high- speed FDAs (Reference 2) focused 1st on driving high speed pipeline ADCs, the more recent introductions have aimed at lower speed devices with much improved DC precision, lower power, rail-to-rail outputs, and negative rail inputs (Reference 7) to support single supply differential drivers to SAR and delta sigma ADC converters. Table 2 shows the single channel, precision, voltage feedback FDAs available in descending SSBW at gain of 1V/V.
There are two somewhat hidden issues in these newer parts contributing to lower phase margin conditions in certain kinds of applications:
- Many are designed to nominal closed loop gain of 1 which is a Noise Gain (NG) of 2 with good phase margin. Adding a feedback capacitor as part of the design reduces the NG to 1 at higher frequencies - nominally giving lower phase margin.
- The Rail-to-Rail output stages often have a complex and reactive open loop output impedance that interacts with both the load and feedback network. It is imperative to break the loop at the inputs so that this modelled Zol sees both the load and feedback network in the LG phase margin simulation (Reference 8). Some, but not all, of the listed devices in Table 2 include an accurate Zol model (Figure 2, Reference 8).
While there has been some earlier work on improving phase margins using FDAs with capacitive feedback capacitors (Reference. 9), here a more detailed Multiple FeedBack (MFB) filter design example will show some added alternatives to improving the phase margin in those designs using the very well modelled THS4551 (Reference 10).
Starting from the 500kHz 2nd order filter, used to drive the 24bit ADS127L01 in Figure 78 of Reference 10, two improvements can be made on the relatively low phase margin latent within this circuit. Figure 8 shows this design target with slightly improved RC solutions where a simulation of the spot noise across the output pins is a quick way to see if there might be a low phase margin at unity gain crossover for the Loop Gain (LG). This circuit has already added those small inside the loop 5Ω resistors which were found to help move the required external Riso to the load capacitor down. The two peaks in the noise at the output pins (before it is filtered by the post RC filter to the ADC) occur first at the noise gain peaking region that always occurs in these MFB filters and then a 2nd peak around 59MHz which is likely due to low phase margin at crossover.
Using the LG phase margin set up of Reference 8, Figure 9 shows a low 21o phase margin for this simple starting point design. Here, +/-2.5V supplies have been used with a centered Vcom voltage at ground for the LG phase margin simulation. The differential summing point sense voltage polarity reports phase margin directly where the THS4551 differential input impedance is pulled outside the inductive break points and placed across the input sensing points.
A common approach (Reference 11) to improving phase margin for inverting designs (like this MFB filter) is to shape the Noise Gain (NG) up over frequency using a feedback capacitor and a capacitor to ground (for an op amp design). This MFB filter already has feedback capacitors as part of the filter design where placing that same value differentially across the FDA summing junctions is nominally shaping the NG up from 1V/V at higher frequencies (due to just the feedback capacitors) to 1.5V/V splitting the differential capacitor into 2 elements to ground at 2X the value in a NG analysis. Making that slight modification to the original LG simulation circuit does indeed lower the crossover frequency raising the phase margin to 32o. That capacitor is connected across the differential sense point connections where they are converted to single ended with is the same as putting it in parallel with the device differential input Z.
This simple approach is not working as well as it does for low output impedance, non-R-Rout, high speed op amps. The very reactive open loop output impedance is still adding excessive loop phase shift at the output pins due to the feedback capacitive load. One simple change to try is to move the MFB feedback capacitor connection from the output pins to be outside the isolating 5Ω resistors. Doing that in Figure 11 indeed works very well to increase the phase margin to 52o.
Click here for larger image
Phase margin with an added NG shaping input capacitor and connecting the MFB feedback caps outside the 5Ω isolating resistors.
Going back to the closed loop spot output noise simulation of Figure 8 with these two small changes shows a much reduced higher frequency noise peaking in Figure 12.
Making these two modifications has also improved the fit to target as shown in the two response curves to the differential FDA output pins shown in Figure 13.
The original circuit of Figure 8 gives that slight response peak at 59MHz and actually missed the ideal 440kHz target F-3dB with only 385kHz. The improved phase margin design of Figure 13 removes that resonance and hits the target very closely with 443kHz F-3dB. Since the RC values are the same in each case, the shift in target shape can probably be attributed to the open loop output impedance seeing the feedback capacitors directly instead of isolated through 5Ωs.
The methods described here to extract the phase margin for a voltage feedback FDA can be applied to any application circuit. In the specific case of circuits having direct feedback capacitors, consider adding small inside the loop isolating resistors then connecting those feedback capacitors outside those Rs. Also, consider adding (at least a placeholder on the PCB) a differential input capacitor to shape the noise gain up at higher frequencies. Many older non-R-Rout designs respond very well to this noise gain tuning by itself. For R-Rout designs, it might be necessary to also include the isolating resistor and connect the feedback C outside that element to isolate the reactive open loop output impedance. It is not always the case that the model captures that effect – even if it is almost certainly in the physical device for R-Rout devices. Next up, extracting parasitic input capacitance for the different high speed amplifiers, what to do if it doesn’t match the datasheets, and how that element gets into the response for different circuits.
References for FDA Stability considerations
- ADI, AD8138, “Low Distortion Differential ADC Driver”, 1st FDA, Introduced March 1999
- TI, THS4509, “Wideband, Low Noise, Low Distortion, Fully Differential Amplifier”
- Planet Analog article “Stability Issues and Resolutions for High Speed Current Feedback Op Amps”, Insight #7”, Michael Steffes, April 7, 2019
- National LMH6554 FDA, “2.8GHz, Ultra Linear Fully Differential Amplifier”
- TINA simulator available from DesignSoft for <$350 for the Basic Plus edition. Includes a wide range of vendor op amps and is the standard platform for TI op amp models.
- Planet Analog article “Stability Issues for High Speed Amplifiers: Introductory Background and Improved Analysis, Insight #5”, Michael Steffes, Feb. 3, 2019
- Planet Analog article “Input and Output Voltage Range Issues for High Speed CFAs and FDAs, Insight #2”, Michael Steffes, Nov. 27, 2019
- Planet Analog article “Extracting Loop Gain and Phase Information from Simulation”, Michael Steffes, Aug. 9, 2018
- Planet Analog article “Improving Phase Margin for Highly Reactive Output Stage Impedances in Op Amp and Fully Differential Amplifier Applications”, Michael Steffes, Sept. 7, 2018
- TI THS4551 “Low Noise, Precision, 150Mhz, Fully Differential Amplifier”
- EDN article “Unique compensation technique tames high bandwidth voltage feedback op amps”, Michael Steffes, Feb. 27, 2019