As operating speeds increase, the effect of the internal impedance at the input nodes become more critical to achieving the desired frequency response. The most common issues revolve around the common mode and differential mode input capacitances for high speed Voltage Feedback Amplifiers (VFAs). While there are always physical input capacitive terms, their data sheet reporting is uneven at best. Assuming a device data sheet accurately reports both elements, then getting those into the public simulation models has also been hit or miss. Here, model testing steps will be shown for the VFA then external adjustments to match reported data sheet numbers will be shown. A couple of example applications that depend strongly on these terms will then be featured. These steps will also be extended to current feedback amplifiers (CFAs) and Fully Differential Amplifiers (FDAs).
Input capacitance model and extraction for VFAs.
All VFAs physically have two common mode input impedance elements on each input to the supplies along with a differential input impedance between the two inputs. Normally, the resistive elements are large enough to be ignored in VFAs. Here, the parasitic input capacitance terms will be the focus where the common mode terms are assumed to be matched on each input pin. Figure 1 shows this model drawing from one of the most common applications that is very sensitive to input capacitance – the transimpedance amplifier (Figure 1, Reference 1). This drawing does not show the Ccm on the V+ input as that is shunted to ground in this case. Also, the Ccm on the inverting input is shown to ground as that is equivalent to connecting it to the supplies for analysis purposes (normally, op amps do not have a ground pin separately from the two supplies).
Typical Transimpedance design analysis schematic.
For loop gain analysis purposes, the transimpedance design needs to consider the Cs of Figure 1. Both the Ccm and Cdiff need to be accurately reported in the datasheet and captured by the public simulation models. Starting with the datasheet reported numbers from the OPA350 (Reference 2) in Figure 2, does the original 1999 TINA (model library in Reference 3) model show these values internally?
One approach to checking the model is to go inside the netlist and search out what is on the input pins. Sometimes a combination of capacitors, protection diodes, and transistors makes that more effort than simply simulating what the model shows. There are always multiple valid approaches to any model testing effort. The first step used here is to isolate on the Ccm element using the approach of Figure 3. This is operating the op amp in a non-inverting gain of 1V/V configuration where a large series input resistor to the V+ input will create a single pole response to the V+ input depending the internal Ccm. That resistor value (in decade steps from the value shown) can be used to adjust for the 2π term to easily take the measured single pole F-3dB back to a 1/(2πRC) solution for the Ccm. This closed loop simulation will be bootstrapping out the effect Cdiff as long as the closed loop op amp bandwidth far exceeds the pole introduced at the V+ input. This same approach can be used for decompensated amplifiers operating at a higher than minimum stable gain and a closed loop bandwidth far exceeding the pole introduced at the V+ input by the source Rs and internal Ccm.
This simple test solves this single pole response to 10μF/2.52MHz = 4pF internally for its V+ input common mode capacitance. Since the gain of 1 closed loop bandwidth at 38MHz is far higher than this input pole, the differential input capacitance is removed from this test by the loop gain. It would appear that a 2.5pF external V+ capacitor to ground is needed to match the data sheet specified Ccm value of 6.5pF.
Numerous efforts to extract the differential input capacitance within the model led to the simple approach of Figure 4. Here, the large feedback inductor closes the DC loop to find a centered DC operating point, then opens up at the first small signal frequency step while the large capacitor is open at DC then shorts out on the first small frequency step. This places the V+ input Ccm capacitance + the Cdiff in parallel as a load on the source resistor. The Ccm on the V- node is shorted out by the large cap in this simulation. Solving for that total C as 10μF/802kHz = 12.5pF. Removing the 4pF Ccm term, the model apparently has a Cdiff = 8.5pF. There is evidence in the phase of a higher zero coming into this simulation. With -41deg at F-3dB (vs. -45deg ideal single pole), this is still approximately accurate. Getting the model to match the 2.5pF Cdiff from Figure 1 requires a -6.0pF element added across the inputs. Fortunately, this negative C (or L, or R) is a feature supported by TINA.
Normally you would expect what V+ Ccm has been added to the model appears identically on the V- input pin. To check that, the inverting input test circuit of Figure 5 can be used. This is essentially the same test as Figure 4 but isolating on the V- input Ccm in parallel with a Cdiff value. Grounding the V+ input removes the positive side Ccm from this simulation. Oddly, this shows lower total capacitance than the previous test with a perfect single pole response as shown by the -45deg phase at F-3dB. This solves out to a total C of 10μF/1.11MHz = 9pF. With the 8.5pF Cdiff in the model, this suggests the apparent internal Ccm on the V- input is only 0.5pF. Adding a 6pF externally to ground on the V- node will be necessary to match the data sheet 6.5pF number in Figure 1. It appears the inverting input Ccm terms was simply added to the Cdiff in this model. That will give equivalent performance vs. having the two terms in most, but not all, application circuits.