Testing the modified OPA350 model in a Transimpedance Application.
The design flow for a transimpedance application (Reference 1) needs the sum of the Ccm on the inverting input and the Cdiff, along with the detector capacitance to set the feedback capacitor to achieve a desired Q in the closed loop response (Equation 3, Reference 4). Taking a test case of a detector source capacitance of 10pF with a desired transimpedance gain of 100kΩ. The 1999 OPA350 TINA model has a true Gain Bandwidth Product of 38MHz with a 1kΩ load. In order to make the test design more sensitive, target a 2dB peaked gain with a Q=1.0. Equation 1 gives a good approximation to the required feedback Cf to hit any design shape.
Putting a Cs = 10pF (diode) + 6.5pF (datasheet Ccm) + 2.5pF (datasheet Cdiff) = 19pF and a GBP = 38MHz with Q = 1 gives a required Cf = 0.89pF. Figure 6 adjusts the 1999 model to match the data sheet (using external C elements) and runs this transimpedance simulation showing a very close 1.7dB peaking in Figure 6.
The net adjustment for the Cdiff + Ccm is 0pF here, so there would be no apparent difference in this application to remove those external adjustments. For all applications, this full externally adjusted subcircuit for this model could be used in any circuit to more accurately estimate small signal response.
However, this OPA350 model (Reference 5) was completely updated in early 2019 to more accurately match the data sheet performance. Stepping through the input capacitance extraction steps shown here indicate this 2019 update exactly matches the data sheet input capacitance numbers of Figure 1 with two 6.5pF common mode input capacitors and a 2.5pF differential input capacitor. The GBP shifted up slightly in this new model to 41MHz. Re-running Equation 1 for the required feedback capacitor to hit a 2dB peaked transimpedance response gives Cf = 0.86pF. Re-running this design with the new model and the external input caps removed with a slight shift in the Cf value, gives the 1.2dB peaking in Figure 7. This is only approximately matching the expected 2dB peaking probably due to the large change in the reactive open loop output impedance going from the 1999 model to this 2019 OPA350 model update.
This example showed only a modest impact from an earlier, less accurate, model to the latest update but illustrates a flow to test any VFA model for input capacitance. In summary:
- There are a surprising number of high-speed VFA datasheets that report no, or only Ccm, input capacitances. That cannot be physically correct, so perhaps a model extraction can be used to define what is in the device. Sometimes these numbers are not in the specification tables, but in the applications text. For instance, the LMP7721 (Reference 6) shows a common mode input Ccm on page 18 as 11pF with nothing in the specification tables. The original 2008 model had no input capacitance in the model, whereas a recent 2019 update shows Ccm=15pF and a Cdiff=5pF.
- Where both CM and DM input impedance lines appear in a datasheet, it is by far the most common case that the Cdiff < Ccm. Where that is reversed, proceed with caution (Reference 7).
- Since the data sheet numbers are usually from the IC designers, those might have the most accuracy. Lacking any other data, use those, and the tests shown here, to validate and adjust the model to match the datasheet.
- While the TINA V11 includes a vast range of industry op amp models, be sure to check if the vendor web site offers an updated version that might have improved accuracy on this, and other, parameters.
The Impact of Input Capacitance on Common Applications
Aside from the transimpedance design example above, many other applications are vulnerable to input C induced issues as well. A very common one would be a simple non-inverting gain op amp using excessively high a resistor values. Continuing with the 2019 updated OPA350 model, Figure 8 shows a simple gain of +2V/V using 1kΩ Rf = Rg values. Even this relatively low selection for Rs is introducing a pole in the feedback loop due the 9pF sum of Ccm + Cdiff. For loop gain purposes those are added. Figure 8 shows a low impedance driving the V+ input. There will be no added response pole due to the V+ Ccm and the source shorts out that element for Loop Gain (LG) analysis. If the source impedance was not zero, the V+ Ccm would be part of the response as both a pole in the response to the V+ input and as part of the divider network to develop the “differential” feedback voltage for Loop Gain analysis.
The relatively high 9pF on the summing junction in this corrected model is giving 2.45dB peaking at 19.7MHz. The original 1999 model showed almost no peaking dropping it into the simulation of Figure 8. And, the datasheet (Reference 2) shows no closed loop response curves suitable to this design. Running a LG Phase Margin (PM) test (Reference 4) on this design gives the 51deg phase margin of Figure 9.
Removing the 9pF at the summing junction increases this PM = 77deg. A common way to improve phase margin in this situation is to add a compensating capacitor across the Rf resistor (Figure 16, Reference 8) as shown in Figure 10. This Cf = 9pF indeed flattens the response out and give a 28MHz closed loop F-3dB. Of course, this depends on knowing what the model is delivering in its internal Ccm and Cdiff. Placing this same 9pF into the LG simulation of Figure 9 gives 75deg Phase Margin (PM).
Another approximate approach to improving the response flatness when the device model is showing a relatively high input capacitance is to reduce the resistor values. Starting from a no summing junction capacitance phase margin case, Eq. 2 gives the maximum Rf to limit the reduction in phase margin from there by no more than 10deg. This equation is approximate in that it is not including the reactive open loop output impedance updated in the 2019 updated OPA350 model.
Ko is the gain (2, here)
GBP is the true model single pole Gain Bandwidth Product in Hz – 41MHz here.
Cp is the Ccm + Cdiff or 9pF for the OPA350 updated model.
Putting those numbers into Equation 2 shows a maximum Rf of 431ohms. Putting the closest E96 values into the LG simulation drops the phase margin from the no input C, 1kohm Rf = Rg, PM=77deg to 63.5deg. Putting those into a closed loop gain of +2V/V simulation of Figure 11 gives a very nice (nearly Butterworth) flat response with F-3dB = 37MHz. This all starts from knowing the model values for the input parasitic capacitors. This example does point to one of the dangers of higher speed devices with higher input parasitic Cs. You can quickly get into a lower phase margin condition with higher R values and to get out of trouble you may need to use resistor values lower than you might want from a power dissipation standpoint.
Higher speed VFAs all physically have some input common mode and differential mode capacitance. Knowing what those are in the vendor models is a pre-requisite to fixing any response peaking issues. Use the steps shown here to test and/or modify the model to datasheet numbers – if available.
Input Impedance Considerations for High Speed Current Feedback Amplifiers (CFAs)
All CFAs use a unity gain buffer from the V+ input to the V- input. The most recent (2018) CFA introduction (Reference 9) shows a detailed input impedance specification in Figure 12.
Input impedance specifications for the THS3491 CFA
High source impedances driving the V+ input will get bandlimited by that 1.2pF input capacitance. That model capacitance can be extracted using the same approach as Figure 3. Make sure to use a feedback resistor at least as high as the recommended value for stability in that simulation. There is not, however, any such thing as a differential input C for a CFA. The inverting input resistance becomes part of the CFA Loop Gain and can be tested in the model as shown in Reference 10.