Most high-speed Voltage Feedback Amplifier (VFA) product developments have focused on the unity gain stable type, with far fewer offerings in decompensated VFAs. Those seem to come with more oscillation risk but can offer improved dynamic range vs. quiescent power. Here, some typical applications particularly suited to a decompensated VFA solutions will be shown with phase margin improvement techniques where needed. A sampling of vendor solutions across different process technologies will show the range of available high speed decompensated VFAs.
What is a de-compensated VFA and why would you use it?
Starting from a typical unity gain stable VFA, to get a decompensated version, IC designers would normally:
- Increase the input stage transconductance – reducing the degeneration resistors - normally lowering the input spot noise voltage.
- Decrease the dominant pole compensation capacitor just in front of the output stage buffer. With the same total supply current, this will normally increase the available slew rate along with increasing the Gain Bandwidth Product (GBP).
Using the same total quiescent current, a decompensated version will have a higher GBP, a higher slew rate, and lower input voltage noise. The initial intent for this type of device was simply to provide higher closed loop bandwidths when operated at higher gains. Using a few simple external design tricks, you can also use these to provide higher Loop Gain (LG) at lower frequencies – which is one path to lowering the harmonic distortion. Figure 1 shows the simplest higher gain application using the decompensated OPA838 bipolar device (Reference 1). This is using the Rf and Rg values from Table 1, Reference 1. Those values were developed solving for the Rf value that gives a total resistor noise power contribution at the output at 40% of the total and considering the added loop phase shift due the Rf|| Rg driving the input pin parasitic capacitance. Lower R values would reduce the total output noise but then start to add meaningfully to the total power consumption over just the 1mA quiescent current for the OPA838. The Rs at the V+ input is added to achieve bias current cancellation for this bipolar input device. That Rs does increase the total output noise and should be replaced by a 10ohm value if DC precision is not a concern.
Running a Loop Gain (LG) Phase Margin (PM) test in Figure 2 shows a LG=0dB at 28.5MHz with 64deg phase margin. This would suggest (Figure 4, Reference 2) a 1.56X28.5MHz = 44.5MHz F-3dB where the actual bandwidth shown in Figure 1 is 58MHz. While the LG = 0dB frequency closely matches the expected GBP of 300MHz divided by the Noise Gain (NG) of 10, quite a lot more closed loop bandwidth is delivered due to the PM<90deg effect. The added F-3dB extension (over Figure 4 Reference 2) is probably due to the > 2nd order Aol model and the reactive open loop output impedance in the model. The feedback LG measurement point in Figure 2 reports phase margin directly with the polarity shown and includes the internal input impedance model elements (Reference 3) along with the Rs element on the V+ input.
Extending inverting operation to lower gains using decompensated VFAs
Moving beyond the simple non-inverting application at higher gains, if the application can use an inverting configuration, a simple external compensation can be used to operate at any inverting gain (including attenuation) applying a de-compensated VFA. Legacy literature (Page 14, Reference 4) also suggests a lead/lag compensation across the input pins (a series RC) to operate at low gains. This works, but does introduce a response zero impairing frequency response flatness and settling time. This simpler two capacitor inverting compensation approach (Reference 5) actually remains 2nd order with no zeroes providing an easily tuned closed loop response. The earlier illustrations using this technique matched theory very well with non-RR output stages having low open loop output impedance. More recent RR output stages with highly reactive open loop output impedances in their models still work, but do not match the simpler analysis in Reference 5 as well.
The general analysis of Reference 5 was later simplified to a closed loop Butterworth target as shown in equations 4 -> 7 in the OPA847 datasheet (Reference 6). The two capacitors in Figure 4 (using the newer OPA838 - Reference 1) are shaping the Noise Gain (NG) up with frequency to achieve a Loop Gain (LG) = 0dB crossover at a high enough NG to maintain stability for this de-compensated device. This does reduce the closed loop bandwidth but retains the full rated slew rate and a low input noise at frequencies below the NG zero frequency. The two key Noise Gains (NG) are the low frequency NG1 and then the higher frequency NG2.
To solve for a nominally Butterworth closed loop response, use Equation 3 to get the Zo – this is physically the projection of rising portion of the NG in a Bode plot projected back to its 0dB intersection.
The actual NG zero frequency will occur at NG1*Z0.
With Z0 resolved, the required Cf will be given by Equation 4
And finally, the required Cs on the inverting node to ground is solved using Equation 5
For devices that do not have a highly reactive open loop output impedance, the resulting closed loop F-3dB bandwidth is approximately given by Equation 6
A graphical interpretation of what is going on with this inverting compensation is shown in Figure 3 (Figure 2, Reference 5). Here, only the dominant op amp Aol pole is shown. Any actual decompensated op amp will have higher frequency poles that will move the true Aol = 0dB crossover away from the ideal projected frequency. However, the LG = 0dB frequency is being pulled way back by the compensation to occur in a region easily modeled as only a dominant pole model.
Bode plot of op amp Aol and the NG for the inverting compensation approach.
To step through an example design, start by picking an Rf that is relatively low to hold its noise contribution down. Select:
a. Rf = 499Ω.
b. Set the target gain to = -2V/V - then Rg = 249Ω.
c. This gives us a low frequency NG1 = 3V/V.
d. Select a target high frequency NG2 > min stable gain of 7V/V at 10V/V.
e. Using the 300MHz GBP of the OPA838, use Equation 3 to get Z0 = 2.25MHz.
f. Then the Z1 in Figure 3 will be 3*2.25MHz = 6.75MHz. Below this frequency the LG is increased by the compensation to deliver lower harmonic distortion.
g. Using Z0 and Equation 4, set the feedback Cf = 14pF.
h. Then using Equation 5, set the capacitor to ground on the inverting input to 127pF, which is reduced by the internal 2pF Cdiff + Ccm, to Cs = 125pF.
i. The approximate closed loop bandwidth is estimated by Equation 6 to be 26MHz.
Figure 4 shows the resulting closed loop responses for different external conditions. Clearly, the two compensation capacitors are required to operate at this lower than minimum stable gain condition. The response shape with the compensation capacitors is peaking more than expected with extended bandwidth. Isolating the effect of the open loop output impedance by using a dependent source (Figure 7, Reference 2) shows a much better Butterworth fit with a 33MHz F-3dB nearly matching the expected 26MHz value.
While the basic idea of this inverting compensation still works with the RR output OPA838, the added poles around the loop due to its reactive open loop output impedance move the resulting closed loop shape off the earlier theory. Decompensated wideband op amps with lower open loop output impedance using a non-RR output design (like the OPA818, Reference 7) will fit the expected shape much better. Figure 5 shows the Loop Gain (LG) simulation of Figure 4. The meter is rotated to report Phase Margin (PM) directly. This 21deg phase margin is much lower than the closed loop peaking in Figure 4 might suggest. Note the full input impedance model and the bias current cancellation resistor on the V+ input to ground are included here to develop the differential feedback voltage. This lower than expected PM, and lower peaking than expected for that PM in the response shape, are due to the OPA838’s reactive open loop output impedance model (Zol). To move closer to theory in the next two examples, a non-RR output decomp JFET device (OPA818) with much lower Zol (Figure 5, Reference 7) will be used.