Editorís note: I found this product solution to be a unique and very interesting solution for designers who need power sequencing especially with a large number of power rails. This product looks like it can make designers work a bit easier and with a faster time-to-market.
Itís no secret that electronics systems are becoming more complex across all industries. It is less obvious how this complexity has infiltrated power supply design. For instance, functional complexity is commonly addressed by using ASICs, FPGAs, and microprocessors to enrich application feature sets in ever-smaller form factors. These devices present disparate digital loads to the power system, requiring a wide variety of voltage rails over a range of power levels, each with highly individualized rail tolerances. Likewise, correct start-up and shut-down sequencing of the supplies is important. The multiplying of the number of voltage rails on a board has made power system sequence design and debug exponentially more complicated over time.
The number of voltage rails required by an application board is a function of the boardís complexity. A power supply designer may face boards requiring only 10 voltage rails, as well as those requiring 200 voltage rails. Sequencer devices usually top out around 16 rails and are designed to easily be applied up to that number. Once the number of rails goes beyond that supported by a single sequencer, the complexity quickly increases, requiring designers to learn the vagaries of each sequencer, and how it can be combined in complex systems.
Often, multiple sequencers are cascaded in high count voltage rail systems, a nontrivial task. In a cascaded system, complexity increases exponentially with a linear increase in the number of voltage rails. Designers have adopted creative methods of cascading sequencers to mitigate complexity, such as using ping-pong mechanisms or sharing the fault and Ďpower goodí status via dedicated digital signals. While these solutions suffice in relatively straightforward sequences, they quickly become untenable in systems that deviate from simple power-up/power-down sequencing.
The ADM1266 solves the problem of complexity with true scalability. It is the latest addition to ADIís Super Sequencer family of parts. Connecting multiple of these devices requires the use of a dedicated two-wire interdevice bus (IDB) to communicate. Each IC is capable of monitoring and sequencing 17 voltage rails, and up to 16 ADM1266 devices can be connected in parallel to monitor and sequence 257 voltage rails, as long as all devices are connected to the same IDB.
The device uses a single master with additional devices acting as slaves. The devices use a parallel architecture in which every single device is connected to the IDB transitions to the same next state, depending on system conditions, ensuring that every one on the bus is in sync. Bus communication is transparent, so the designerís experience is the same in creating a sequence for a single IC as it is for 16 of these devices. A significant advantage to this system is that designers only need to learn how to use one device for both simple and complex designs, eliminating multiple learning curves for different devices. Cascading multiple devices is as simple as connecting them to the same IDB, as shown in Figure 1.
Modern sequencers must do more than just monitor voltage rails, they must also react to digital signals. Traditional time-based sequencers have fixed signals with a dedicated outcome and limited functionality.
Letís take an example of a motherboard with an optional daughter board. A daughter card detect signal is monitored by the sequencer: when this signal is present, the sequencer brings up the voltage rails present on the daughter card; when the signal is not present, the sequencer continues with the motherboard sequence procedure, finishing with the power good state. Such a daughter card detect signal is not available on most traditional sequencers. Additionally, such requirements change based on the application, and can be addressed with general-purpose input output (GPIO) pins.
Another example involves powering an ASIC and an FPGA wherein the system requires that the ASIC be completely powered up and running before the FPGA is powered. In this case, the sequencer brings up the ASIC supplies in order, then waits for a digital power-good signal from the ASIC. Once the ASIC power good signal is asserted, it waits 100 ms before it continues to power the FPGA. An event-based sequencer is required to produce this complex sequence. In a system with multiple sequencers, it is important that the event information on one device is shared with the other devices on the board so that they act in unison.
Voltage monitor OV and UV comparators, digital signals like GPIOs and PDIOs, timers, variables, and messages from the IDB all feed into the feature-rich ADM1266 sequence engine and trigger events. The user can easily create complex state machines that monitor a variety of events and take appropriate actions.
Accelerating System Design
Traditionally, the user experience of designing a power sequencing system using a single sequencer is vastly different than that for a system requiring multiple sequencers. That is, a design with a single sequencer for 16 voltages is often straightforward: the designer uses a software graphical user interface (GUI) to configure each voltage rail and their sequencing. The process is generally a manual selection/setting process repeated for 16 rails. Now imagine a design with five sequencers and 80 rails. Manually configuring 80 rails using a GUI is time consuming and prone to human error. The designer must also determine how to best cascade multiple devices and assign the resources of the five sequencers to the 80 voltage rails. Most software-assisted design tools do not actually assist. The user must understand the specific functions of the sequencer IC and explicitly tell it what to do via the GUI, creating a fairly steep learning curve for each project.
This IC takes a different approach. It is configured and debugged using PC-based ADI Power Studio,ô which does far more than configure the various settings of the device. ADI Power Studio is a complete development and debugging tool that assists the designer in realizing a robust sequence. It enables the designer to approach the power system at a much higher level than traditional GUIs. For instance, built-in wizards enable the designer to set up and configure 80 voltage rails in a few minutes, a task that would take a few hours if done manually. Figure 2 and Figure 3 show some examples of the interface.
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One step configuration of an entire system. The system rails wizard leads the designer through the process of configuring an entire sequence using the same interface regardless of the rail quantity. Note the user-defined custom rail names, making it easier to recognize individual rails on sight.
The designer starts by creating a virtual state machine to meet the requirements for the system. In a single sequencer design (≤17 rails), the virtual state machine of the GUI simply matches the state machine of the sequencer. As more sequencers are added, the virtual state machine deviates from the individual sequencer state machines, requiring additional steps in the state machine as devices communicate various events with each other.
For example, a designer monitors two voltage rails on Sequencer 1 and two voltage rails on Sequencer 2. The design requires that if any of the four voltage rails sees a fault, then everything shuts down. In practice, since there are two devices, they will have to share a fault signal between them. The systemís virtual state machine and the state machines for the individual devices are shown in Figure 4.
Virtual state machine vs. device-level state machine.
As the number of rails and the sequencing requirements become more complex, the systemís virtual state machine and the state machines at the device level increasingly deviate. The designer knows what he or she wants to happen, but must make the sequencers work together to make it happen, a time consuming and usually buggy process. ADI Power Studio automates much of the state machine creation process. The user designs the virtual state machine using the GUI, while the compiler in the ADI Power Studio handles the complexity of communicating between various sequencers. This enables the designer to create complex state machines using a flexible, intuitive process.