Validating an IC design comes with unique challenges and considerations. This article provides a refresher on the overlooked or forgotten fundamentals behind commonly used practices, techniques, and rituals to validate the design specifications in the lab. Though the article refers to bench testing, most of the concepts apply to both automated test equipment (ATE) or a bench test platform.
Typical Bench Setup
Typical Bench Setup Diagram
A typical bench setup consists of:
- PCB board which houses the device under test (DUT).
- Bench-top instruments to force/sense V/I and provide digital patterns for generation/capture, as well as a scope for visual inspection for timing tests.
- Software to control the DUT board/instruments and generate reports in an automated setup (optional). Automation ensures the consistency of setup configurations, provides reliable measurements, and reduces human error in post processing/data-logging.
A typical test PCB contains connectors to route external sources in/out, active and passive components for signal conditioning/switching, and programmable devices to support automation. One or the other passive components (R, L, and C) is present in every PCB, and most commonly used active devices are operational amplifiers (op-amps), transistors, and diodes. In this article, we’ll focus on the active role played by these PCB passive components and the impact on DUT measurements.
A capacitor is primarily a charge-storing device that stores electrostatic potential energy in the electric field created between two conductive materials separated by a dielectric. The capacitance of any capacitor depends on its geometrical construction and the type of dielectric material. For example, a parallel plate capacitor’s capacitance (C) is given by C = εA/d, where ε is the permittivity of the dielectric material, A is the cross-sectional area, and d is the separation distance between the two terminals.
For a capacitor charged to a given potential difference (V), a material with higher permittivity will hold more charge in a smaller form factor. Capacitors are categorized into different categories, based on the type of dielectrics, voltage ratings, current handling capacity, form factors, etc.
Types of commercially available capacitors based on dielectric materials.
The most commonly used surface mount (SMD) capacitors in a typical lab setup are ceramics and electrolytic types:
- Ceramic capacitors are most commonly used in lab evaluation boards due to their low ESR and linear distribution of voltage across the terminal. Below tables show the different classes and standard nomenclature of SMD ceramic capacitors.
Primary differences between two commonly used SMD Ceramic Capacitors.
EIA-RS-198 naming convention followed by Class 1 SMD ceramics from 25oC to 85oC.
EIA-RS-198 naming convention followed by Class 2 SMD ceramics.
Based on Table 3, the C0G capacitor is the best in its class with zero temperature drift and a tolerance of +/-30ppm/K. Similarly, a X7R capacitor can be decoded to have a tolerance of +/-15% over an operating range of -55oC to 125oC. A Class 1 capacitor may look like an obvious choice for most applications, but usage in small-space applications could be limited by its volumetric inefficiency compared to a Class 2 X7R.
Though ceramic capacitors have the advantage of temperature stability and a high dielectric constant, they do have poor DC bias characteristics (the rate of change in capacitance with regard to change in applied voltage). A Class 2 capacitor can experience as much as 50% capacitance derating over a DC bias range of 0-6V, so it’s a good idea to use a 2-3 times higher capacitor value if it is a system requirement to maintain a minimum capacitance for a DC bias voltage range.
- Electrolytic capacitors use oxide as their preferred dielectric while the cathode is composed of electrolyte. For example, aluminum electrolytic capacitors use aluminum oxide as their dielectric and manganese oxide as a cathode. Tantalum capacitors have more permittivity than the aluminum ones and, hence, offer more capacitance in a similar footprint than the aluminum ones. In general, surface-mount electrolytic capacitors have more ESR and ESL than ceramic, but their capacitances can go to 1000μF or more. It is common practice to use polarized tantalum capacitors right at the PCB main power connector, where it acts as a circuit breaker in case the user misconnects the positive and negative supplies.
Most PCB designers deal with the capacitor in the below applications:
- Bypass capacitors are placed on DUT supply pins and reject any sudden changes in voltage across their terminals, thus filtering the AC ripple on the supply rail and providing a clean DC voltage. In a typical PCB design, one would use bigger electrolytic capacitors (300μF) at the board power junction and use low ESR/low-footprint multiple ceramic X7R/X5R (Class 2) in parallel physically close to the DUT supply pins. It is universal practice to place a high-value (1-10μF) and low-value (1-100nF) capacitor to bypass the low frequency and decouple the most common radio frequencies, respectively. For high-frequency noise decoupling on the source line, one needs to consider ceramic capacitors as RLC circuits (parasitic ESL, ESR with negligible leakage resistance) and calculate the capacitor value to set the ESR-ESL-C to the resonant frequency specific to the hardware requirement. At this resonant frequency, the inductive and capacitive reactance cancel each other, thus providing the lowest impedance (ESR) path to the ground.
- The bypass capacitors should be placed as close as possible to the DUT supply pins to minimize the trace parasitic inductance between the capacitor and DUT pins. Though COG capacitors seem to be the obvious choice for this application due to their excellent temperature drift and superior DC bias characteristics, it is difficult to find high capacitor values (1-100μF) in the smallest 0204 package In such a situation. As a result, one is forced to choose X7R for a smaller form factor in order to place it in a tight space close to the DUT. Figure 2 illustrates the change in a 24-bit delta-sigma ADC) PSRR measurement due to absence or physical placement of the bypass capacitor away from the DUT (2 inches) and closer to the DUT (0.2 inches).
FFT of MAX11254 ADC output conversion codes shows the AC noise magnitude from the supply.
- Charge reservoir capacitors are extensively used in signal-conditioning products like successive approximation register (SAR) ADCs. The external charge reservoir capacitor should be at least 20 times the internal sampling capacitor (CS), which helps in charge transfer during the acquisition phase. This strategy limits the drop of the sampled voltage to 5% and helps to settle the ADC within 0.5LSB during the acquisition time (tacq). A typical value of an ADC internal sampling capacitor is ≅ approximately 50pF, which makes a 1nF C0G SMD capacitor an ideal candidate as an external filter capacitor. Based on the resolution (N) of ADC, the minimum number of time constants required to settle to 0.5LSB is (N+1) *ln(2). This constrains the filter resistance to R= ( tacq/(0.693*[N+1]*20*Cs), assuming that the settling is limited by the external filter. The combined RC filter sets the bandwidth of the input AC signal and the driving op-amp.
- Compensation capacitors are used to stabilize high-performance op-amps while, for instance, driving capacitive loads much bigger than the specified maximum load. Compensation capacitors are used for in-loop compensation techniques, which help to counteract the effect of the additional pole introduced by the output load capacitor and the output impedance of the op-amp. This helps in achieving -20dB/decade slope at the crossover frequency. When an op-amp tries to drive a CL >> CLmax, the output will oscillate due to instability caused by a shift of the output pole caused by CL pole as shown in Figure 3.