How Stable is your Op Amp or FDA design?
One of the most important aspects of any end system design is to understand and improve (if necessary) the nominal phase margin for each stage. Since the early days of op amp development, analyzing the Loop Gain (LG) for Phase Margin (PM) at LG=0dB crossover has been a fundamental part of the designer toolkit (Reference 1).
Tracing the small signal response through the device’s open loop response and then back through the feedback network to where the error signal is formed at the input will give the LG around the loop where the critical assessment is how much phase shift has occurred around the loop at the frequency where the total LG=1V/V (or 0dB). If that phase shift is at or greater than 180deg, then the loop is unstable. Normally, designs should not ship with greater than 150deg phase shift around the loop, or <30deg phase margin. One new aspect to this analysis is the highly reactive open loop output impedance for today’s Rail-to-Rail (RR) output designs. Early op amps had low open loop output impedance whereas many recent RR devices show a strongly frequency dependent output impedance. This open loop output impedance divides against the load in parallel with the feedback impedance to introduce additional attenuation and phase shift into the loop. Even relatively simple circuits like Figure 1 can get into phase margin trouble due to this effect. This simulation is using TINA (Reference 2) to execute a wide frequency range closed loop small signal response.
Gain of 3 with 850kHz feedback pole and simple differential 500Ω load.
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This single-ended input to differential output FDA circuit is using a very low power, wideband, voltage feedback THS4551 (Reference 3) device. While the desired 850kHz low pass pole is being produced by the feedback capacitors, looking further out in frequency shows a disturbing resonance at 165MHz. This circuit is in fact oscillating due to the highly reactive open loop output impedance of Figure 2 interacting with the feedback impedance and due to those feedback capacitors reducing the noise gain (1/β) to 1V/V at higher frequencies. To see the results of Figure 1, it is imperative that the correct open loop gain and phase response along with the open loop output impedance be incorporated into the vendor model – as it was for the THS4551.
THS4551 open loop differential output impedance (Figure 68 in Reference 3 data sheet link below).
Setting up for a Loop Gain simulation.
Any open loop simulation needs to first establish a DC operating point for the device that is usually midscale on the power supplies. One common approach is to add a DC level to the input AC signal that exactly centers the device output voltage where a small signal AC simulation can then be run. While possible, finding that exact voltage to counteract the device DC offsets can be a tedious affair. A faster approach uses extreme L and C values to first establish a centered DC operating point then provides a step impedance shift for the AC simulation. There are several places to break the loop for this simulation where the preferred “input” break point is shown in Figure 3. Several added elements are circled in Figure 3 that aid in setting up and running this simulation. Simulation setup comments:
- The power supplies are split on +/-2.5V where the output common mode control (Vocm) for this FDA type device is set midscale at ground.
- The 9.97kH feedback inductors provide a short at DC then immediately open up on the first small signal AC frequency step point. This DC short ensures the FDA I/O pins all operate at DC ground from the output Vocm control loop.
- The 9.97kF input capacitor injects the small signal AC stimulus while opening up at DC to allow the feedback inductor to set the DC operating point.
The simulation operates to inject a differential small signal stimulus at Vinn and Vinp which then gets gained up by the FDA open loop gain (Figures 66 and 67 in the data sheet of Reference 3), attenuated and phase shifted by the open loop output impedance into the total load seen by the output, then divided down and phase shifted back to the differential measurement points at Voutn and Voutp. This stimulus and measurement is exactly the Loop Gain needed for a phase margin assessment as shown in Figure 3. There, the LG magnitude is plotted on top where the 0dB crossover is located at 170Mhz. Then the lower phase curve is probed at the same frequency to show an excessive -185deg phase shift around the loop.
Loop Gain simulation for the circuit of Figure 1 with the loop broken at the input nodes.
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The circled elements are required (or help) DC operating point convergence or simulation issues.
- The differential stimulus needs a DC path (10MΩ) to ground as they only connect into a DC isolated point.
- The 100Ω in series with the inductors help DC convergence and reduces “numerical chatter” in the AC simulation.
- Similarly, the odd values on the L and C along with the small 0.2Ω output R’s reduce “numerical chatter”. Without this approach, more complicated models like the THS4551 often show a “noisy” AC simulation.
- Most importantly, whenever a loop is broken like this to see the LG, impedances that are now inside the isolating LC, but would normally be part of an actual loop gain response, need to be brought outside the LC isolation and placed manually where they would normally appear. Breaking the loop at the input nodes only requires the specified differential input impedance to be added manually across the Loop Gain measurement points (normally the summing junctions in a closed loop sim) as shown in Figure 3.
The Loop Gain simulation of Figure 3 is in fact showing 185degrees around the loop at LG=0dB at 170Mhz – very near the closed loop response peaking of Figure 1. This LG simulation has confirmed the simple circuit of Figure 1 is in fact unstable. One added useful result out of Figure 2 would be to report the loaded open loop gain and phase for the THS4551 model by placing a differential meter across the 500Ω load resistor.