**Locating the source of low phase margin**

Even the simple circuit of Figure 1 seems to be suffering from a low phase margin condition as described in Reference 1 with a sharp resonance at 165MHz. It is important, even in lower speed signal path applications, to check higher frequencies for trouble.

**Figure 1**

**Wideband small signal simulation using the 150Mhz THS4551 FDA.**

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The poor phase margin here is a combination of factors. The inductive open loop output impedance at higher frequencies (Figure 68, Reference 2) reacts with the feedback capacitive load to create significant phase shift right at the output pin voltages. The feedback capacitor also shapes the noise gain back to the differential inputs down to 1V/V at high frequencies extending the Loop Gain (LG) =0dB crossover out high enough in frequency to find a 185^{o} phase shift around the loop at crossover. Simply removing those feedback capacitors shows a stable result in Figure 2. This signal gain of 3V/V is a noise gain of 4V/V showing a bit of bandwidth extension to 45.5MHz over a simple 135MHz Gain Bandwidth Product (GBP) divided by 4 expectation of 33.7MHz. There is also no hint of stability problems at higher frequencies as there is no sharp peaking in the response.

**Figure 2**

**Simple gain of 3 circuit with no feedback capacitors. **

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Going back to a feedback pole at 800kHz, whether this causes a problem or not also depends on the load. Changing to a more typical Successive Approximation Register (SAR) driver RC load (Reference 3, driving an 18bit, 2MSPS SAR) shows a lower resonant peaking at a much lower frequency - but probably not oscillating. The much heavier load at lower frequency has interacted with the open loop output impedance to attenuate the available feedback voltage at a much lower frequency than the 500Ω load. This has the effect of pulling back the LG=0dB crossover frequency to where the higher order poles of the THS4551 open loop gain (Figure 66, Reference 2) have not added as much to the loop phase shift. Another way of saying this is the loaded Open Loop Gain (Aol) response for the THS4551 shows a much lower frequency LG=0dB crossover. Note the measurement point here is still across the FDA outputs – not the final 1nF load. The instability potential is in the FDA and looking at the filtered response to the load often masks problems – both in simulation and on the bench.

**Figure 3**

**Bandlimited gain of 3 circuit with heavy RC load.**

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Setting up this circuit in the LG simulation of Reference 1, show a LG=0dB phase margin at 49MHz of 15^{o}. So, while this is not oscillating, some work to improve the phase margin would be warranted. The approaches shown will apply to any external combination of loads and feedback networks (including Rauch or Multiple FeedBack [MFB] active filters) that might be putting the device into a low phase margin condition. We will continue with the RC loaded example of Figure 4 as a more real example in a data acquisition application.

**Figure 4**

**LG=0dB phase margin extraction for the circuit of Figure 3 showing 15** phase margin.

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**Circuit options to improve phase margin while retaining the desired amplifier operation**

Since we know the reactive open loop output impedance is part of the problem, simply adding inside the loop output resistance can often improve the phase margin quickly. This has the effect of reducing the phase shift in the output voltage before it gets fed back to the inputs through the feedback network. Simply trying 10Ω inside the loop gives the 34^{o} phase margin of Figure 5. These resistors have proven to be more effective if the feedback capacitor is connected on the output side of them.

**Figure 5**

**Improved phase margin solution using inside the loop output resistors. **

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Adding these resistors inside the loop should be done with some caution as they will reduce the available output voltage swing in some cases. Keeping these relatively low (< 20Ω) will limit that degradation. While this may be enough in this case, there are other application circuits that need more phase margin improvement.

The other issue reducing phase margin in this circuit is that the feedback capacitor is shaping the noise gain over frequency to 1V/V. Most FDAs are nominally designed with equal gain and feedback resistors to give a signal gain of 1 and a noise gain of 2V/V when no feedback capacitor is in place. That nominal resistive loaded design point usually targets a phase margin between 40^{o} and 60^{o}. A LG simulation using all 1kΩ resistors shows a 47^{o} nominal phase margin design for the specification set point used in the THS4551 datasheet (Reference 2).

**Figure 6**

**Nominal phase margin simulation for the datasheet specified gain of 1 with all 1kΩ resistors**

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