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Michael Steffes

DC precision considerations for high speed amplifiers

Michael Steffes
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TucsonMike
TucsonMike
12/5/2018 9:53:52 AM
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Re: Good read
Hey Soufiane, 

It is not just "modern" designers that approach decomp parts with some trepidition. It has always been uphill from the first decomp part I was involved in (the CLC425) to these most recent blazing fast decomp VFA like the OPA855 (8GHz GBP). If you are tasked with a transimpedance design, most designers recognize the need for decomp and deal with it. Otherwise, it is a tough sell even with clear input noise and LSBW advantages. There are certainly added stability risks - but good models can mitigate those. Looking industrywide, I would say LTC has made a commitment to decomp (even more than I have) while Maxim recently spun out a series of decomp CMOS devices. Nice knob to use in product development if you understand the tradeoffs. 

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soufiane_ben
soufiane_ben
11/30/2018 7:26:15 PM
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Newbie
Good read
Hi Michael:

I think some designers should start by selecting the "right" process. There are compimentary processeses which lend themselves better for optimized speed/power ratios. On the other hand, most "modern" engineers seem to fear the idea of a decompenated op amp, think OP37 which is still one of the best decomp op amps ever made in my opinioon. 

I think that soon we will see increased needs for high speed and DC precision, this is particularly true for T&M and automotive but I can also see this need in medical instrumentation for instance. 

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Modern Rail-to-rail (R-R) output stage op amps, or fully differential amplifiers (FDAs), can sometimes get into a low phase margin condition for relatively simple circuits. Using the phase margin simulation test of Reference 1, a few simple external phase margin improvement methods will be shown. These tests and fixes are best done in simulation prior to board layout. Where the device model for a R-R output device is perhaps not including the higher frequency reactance, places for these tuning elements might be put into the board layout as a hedge against future stability problems.
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