yes Scott, I found your book on Amazon as well, will need to get that ordered the next time I can bundle a few more things into an Amazon order. I have run the OPA683 gain of -1V/V using Rf=Rg closed loop (55deg phase margin from peaking) in TINA, and then a single pass, break the loop at the input, LG sim with the inverting input Z model as an LR I extracted from simulating the TINA model. It matches perfectly at 55deg phase margin. I do have the model running with the two pass Middlebrook approach, but have not yet worked through how to massage that sweep through Eq. 8 in this recent Sergio article. Incidently, if your book changes that denominator to a -2 instead of +2, as near as I can tell stepping through Sergio's material - it should be the +2 that shows up in all lit I have found.
Glad to hear the reference to Tuinenga's book was of use. I also found his analysis of the Mddlebrook technique rather compact so decided to work through it myself. You can find the analysis in my book ISBN13 978-0-521-68780-5, section 5.14 if it is of interest. I have found the link to the Franco article and got a copy.
Hello Man21 again, I did get that book and indeed Paul shows that "Middlebrook" based approach as a LG sim approach. It is pretty terse and I could not make much out of it - fortunately, Dr. Sergio Franco just posted a great discussion of this on EDN comparing a breaking the loop approach (called Rosenstark's - news to me?). Apparently, what we have been doing is an approach attributed to Rosenstark where we take advantage of the dominant 1/T term to only do one simulation. Can't attach that article link but it is on EDN posted Dec. 26. I have been working through the much more useful and detailed steps shown there for the middlebrook approach (inserts a test voltage and then a test current at a node without breaking the loop) and indeed that equation you questioned in Paul's Spice book is in fact correct - pretty odd looking and not computationally obvious - going off to see if I can replicate this approach with my vast range of CFA models (will use the OPA683 in this case, it is a transistor based model - most accurate). I am hopefull I can get that two pass approach (Middlebrook) to match my simpler break the loop with one pass results - here's hoping!!
Thanks Man21, I vaguely recall this technique and it is probably quite valid as well. There are usually multiple ways to tackle these issues. I could not find a description of what he was doing there, but I suspect he is just solving backwards for the LG inside the full transfer function. So if you have gain phase info closed loop you should be able to dump that data out into some code that will solve for the loop gain. That would be more steps, while the solution we actually use shown in the article is pretty quick and should give the same results. I may buy that book though, seems like a good addition to my library - thanks.
Paul Tuinenga in his book SPICE: A guide to Circuit Simulation and Analysis Using PSpice (section 6.9, p59, Plotting Loop Gain, in my 1998 edition) develops a technique for determining loop gain in a closed-loop circuit without having to break or alter the circuit. It would be interesting to see if that approach produced similar results to those in the present article. It may be noted that my version of Tuinenga's analysis results in a small difference in his final equationon for T on p63 with -2 rather than +2 in the denominator.
Modern Rail-to-rail (R-R) output stage op amps, or fully differential amplifiers (FDAs), can sometimes get into a low phase margin condition for relatively simple circuits. Using the phase margin simulation test of Reference 1, a few simple external phase margin improvement methods will be shown. These tests and fixes are best done in simulation prior to board layout. Where the device model for a R-R output device is perhaps not including the higher frequency reactance, places for these tuning elements might be put into the board layout as a hedge against future stability problems.