Maximizing output power from PLL synthesizer high-frequency open-collector outputs

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Maximizing output power from PLL synthesizer high-frequency open-collector outputs 1/18/2019 Image 1 of 6 Next > Figure 1 Typical open-collector output with a 50 Ω pull-up Image 1 of 6 Next > Return to Article comments Newest First \| Oldest First \| Threaded View [close this box] AaronHe 3/13/2019 3:24:59 AM User Rank Newbie About the pull-up component Hi Dean: How about set the pull-up components as an inductor parallelled with a resistor for example 50 ohm. Choose the inductor value big enough at the working frequency to make the parallelled impedance is almost same as the resistor. And this added inductor will remove the DC voltage drop which could guarantee the output signal will have full voltage swing. Reply Post Message Messages List Start a Board Login 50% 50%		More Blogs from Signal Chain Basics Brushless-DC motor systems for the uninitiated 2 comments Most people are not familiar with electromechanical spinning. My goal here is to attempt to explain brushless-DC motors simply Integrated RF-sampling transceivers enable fast frequency hopping, multiband and multimode operation The latest direct radio frequency (RF)-sampling transceivers provide a number of powerful capabilities that enable advanced system features like multiband and multimode operation, as well as frequency translation and fast frequency hopping. Overcoming common challenges driving an amplifier with a photodiode 1 Comment A transimpedance amplifier (TIA), which takes the current from a photodiode and converts it into a usable voltage with low output impedance, can provide effective gain for a photodiode signal. Driving the reference input on a SAR ADC In this article, I’ll provide an overview of SAR ADC reference input behavior and reference input drive circuit topologies More from Signal Chain Basics flash poll All polls educational resources How to Reduce Control Panel Costs Using IEC Devices and Busbar Systems Verifying the True Jitter Performance of Clocks in High-speed Digital Designs Verifying Additive Phase Noise and Jitter Attenuation of Plls in High-speed Digital Designs High Power Monolithic Silent Switcher 2 Regulators Meet CISPR 25 Class 5 EMI Advancing the Art of Parasitic Extraction True Costs of Process Node Migration Physical Design Data Validation from Cell Design to Tapeout uModule Isolation Solution for High Resolution 1Msps ADCs Reads Data at 100MHz, Serves Multiple ADCs Addressing the Challenges of IoT Design Industrial IoT: Where is Silicon Valley? Smartphone Innovation Ignites IoT Creativity Boost PROFIBUS RS-485 Robustness with GMR Isolation 560V Input, No Opto Isolated Flyback Converter 60V Buck-Boost LED Driver with Up to 98 Percent Efficiency Has Internal PWM Dimming and Spread Spectrum Solve Data Acquisition Compatibility Problems by Combining Features and Performance Wireless Sensor Networking for the Industrial Internet of Things Industry's First 0.8uVRMS Noise LDO Has 79dB Power Supply Rejection Ratio at 1MHz 1.4GHz Low Jitter PLL with Clock Distribution Solves Difficult Clocking Problems Best Practical Jitter Tolerance Testing with MP1800A TI Vision SDK, Optimized Vision Libraries for ADAS Systems Challenges in Temperature Sensor Measurement Solved by Precision Temperature-to-Bits Converter New Linear Regulators Solve Old Problems Dynamic power path management in battery chargers: a highly integrated implementation uModule Buck-Boost Regulators Offer a Simple Solution for Wide Input/Output Voltage Range Applications RF/IF Amplifiers with OIP3 of 47dBm/50dBm at 240MHz Ease Implementation, Guarantee Performance follow Planet Analog on Twitter Tweets about "from:PlanetAnalog OR #PlanetAnalog OR @PlanetAnalog" like us on facebook our partners