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Hey Loren, nice post -yea the first pass at getting Cf=0.175pF seemed a low.
I am guessing the reason the original calculation for Cf was too low was the unity gain closed loop bandwidth of 1.8GHz was used in Eq. 2 where that should have been the GBP, more like 900MHz - Eq. 1 is implicitly solving to place the feedback pole at Fo. that will give a Q=1 and likely the final Cf shown was slightly increased to empirically reduce the peaking (1.25dB) from that condition.
I touched on these issues a bit in a new blog showing up on PLanet Analog, Feb. 3, 2019.
How to generate the open-loop SPICE simulation curves: Open or “break” the loop while injecting a small signal into a high-Z node and look at the response at different points in the loop
The PLL architecture is an effective approach to creating very linear ramping waveforms that are useful for radar applications. That being said, one consideration is how fast the ramp can change and still have the PLL track it. The loop filter needs to be able to allow the frequency to slew fast enough, and you need to take measures to avoid cycle slipping
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