In the previous installment of this series, we looked how the differential input configuration of an ADC can improve its performance. This installment talks about another ADC specification that affects the conversion accuracy: input impedance. Input impedance is a critical specification and must be understood correctly, for if it is not appropriate as required for the given signal source, an additional buffer stage may be required to accurately measure the signal.

**Input impedance**
The input impedance of an ADC is defined as the impedance seen by the signal connected to its input terminals. The aspect of input impedance that matters the most is to achieve the impedance matching requirements while interfacing a signal to it. Without the proper attention to this aspect, the ADC might not see correct signal level at its input, resulting in distortion of the signal and leading to erroneous measurements.

This becomes even more critical when the input impedance of the ADC is low and the source is not able to drive the ADC’s input to charge its input capacitor to the required voltage in the given time. There are primarily two kinds of input stages of an ADC: buffered and unbuffered.

**Buffered ADC:** Many ADCs have a built-in buffered input stage. With such an ADC, the buffer stage offers high impedance to the signal being measured. This buffered input stage prevents any drop in the voltage of a signal connected to the ADC. Another advantage of a buffered input stage is that it offers almost constant impedance at all input signal frequencies.

However, there are some negative effects of buffered input ADCs. The buffers might introduce an offset as well as add to the non-linearity of the ADC. Care must be taken to compensate for these side effects if one chooses to go with buffered input ADCs in high-precision applications. Another downside of using buffered input ADCs comes in form of the current consumption of ADC. In some applications, where it is not really needed to have a buffer stage at the input, using an ADC that has a buffered input stage adds unnecessary overhead when it comes to the power budget of the system. Input buffers can significantly increase the overall current consumption of ADC, and this may prove to be unacceptable for low power applications.

**Unbuffered ADC:** These ADCs are the ones that are the primary topic of discussion while talking about an ADC’s input impedance and source impedance matching. ADCs available in most mixed signal devices lack a buffer stage. This type of ADC needs a careful consideration of input impedance. Unbuffered ADCs have a switched capacitor-based input stage. The input impedance for an unbuffered ADC can be modeled as shown in **Figure 1**. The values of R and C can be found in the datasheet of the ADC. One should be careful when evaluating these values because the values may depend upon a number of factors such as resolution, input range, and input configuration (e.g., single-ended versus differential), to name a few.

**Figure 1**

Model of ADC input impedance

**Figure 2**

Simplified switched capacitor based sample and hold circuit
As we can see in **Figure 1**, the input impedance of an ADC is not purely resistive. A switched capacitor input is basically the sample and hold stage of the ADC. **Figure 2** shows the simplified sample and hold circuit. The capacitive part of the input impedance originates primarily by virtue of the sampling capacitor (C_{SAMPLE} in Figure 2) from this circuit. The figures make it clear that the effective input impedance of an unbuffered ADC varies with the frequency of input signal. This relation is given by equation (1) below:

One may think that input capacitance (C_{in}) does not matter for DC signals. This is only partially correct. For DC signals, once the sampling capacitor is charged, only the input resistance matters. However, at the time when the input shifts from one level to other, the settling time will depend upon the sampling capacitor and input resistance. Generally, this capacitor is small enough so that the voltage at the capacitor follows the input voltage almost instantaneously. However, while using the ADC with signals that have very weak drive strength, such as piezoelectric sensors, the charging time of the capacitor may become relevant. In such cases, a buffered ADC is useful.

Another subtle detail worth considering while dealing with an ADC’s input impedance is that the datasheet specifications are the resistance and capacitance of an individual input terminal with respect to ground. This is very different from the impedance that a differential signal would see when an ADC is operated in differential input configuration. In order to estimate the differential input impedance for impedance matching purposes, one needs to measure the differential input impedance at the desired signal frequency. This can be measured by performing s-parameter analysis at the input of ADC using a network analyzer.

A final consideration for the input impedance of an unbuffered ADC is the variation of its input impedance at different times. In these ADCs, different switches are ON during track and hold modes. This translates to different input impedance when the input circuit is in track mode and when it is in hold mode. The ADC sees the input signal only during the track mode since the input is more or less isolated during hold mode. Therefore, only track mode impedance is of interest when it comes to the impedance matching circuit. ADC datasheets will typically provide track mode impedance values.

To make accurate measurements using unbuffered ADCs, if the source cannot supply the required current to handle the ADC’s low input impedance, another signal conditioning stage will be required between the signal source and the ADC.

In the next installment of this series, we’ll talk about impedance matching.

**About the authors:**

**Sachin Gupta** *is working as Senior Applications Engineer in the PSoC 1 Applications group with Cypress Semiconductor. He holds a Bachelor’s degree in electronics and communications from Guru Gobind Singh Indraprastha University, Delhi. He has several years of experience in mixed signal application development. He can be reached at sgup@cypress.com.*

**Akshay Phatak** *is an Applications Engineer with Cypress Semiconductor. He holds a Bachelor's degree in electronics and telecommunications from the College of Engineering, Pune, India. He likes to work on mixed-signal embedded systems. He can be reached at akay@cypress.com.*