Design Margin is a term that engineers use, sometimes rather casually, when describing how "close to the edge" a design is. The margin might relate to power dissipation in a component or the voltage applied to a device with respect to its absolute maximum rating. Sometimes the margin is a nebulous quantity and it isn't clear how much margin exists above a customer supplied specification. For someone doing a design, this can be a significant problem. It takes a significant amount of study and analysis to determine the true design margins that are required. As designers, we often find that to do a given function requires significantly more margin than what the customer assumed (based on their specifications).
This can be especially true for RF susceptibility. For example, assume that someone is doing a design related to a fuel system that may be subject to an RF field of strength to be specified during the design process. The customer may supply a specification that is boiler plate from all their other designs. At first look, it may seem fine. However, upon further study, one may determine that RF from more than one source can combine to cause components to heat to a flash point. This is very different from RF jamming a single susceptible channel or IF. This can mean that significant margin can be required to truly be safe. Furthermore, foreign countries and military installations can significantly exceed civilian limits under certain events/conditions. What started out as, for example, a 400V/m susceptibility specification might end up at 3200V/m -- or even higher -- design margin level for one’s equipment in order to have a safe design.
Often broad-band digital signals are the same way -- there is a very low energy per bit, and multiple RF sources can combine to cause small noise events that disrupt individual bits. This is very different than most susceptibility specifications and tests, which test one interference channel at a time. Here again, often much margin is required or bit errors will start to significantly degrade throughput at some possible point in the future. Other means of dealing with the interference may be required, including ECC/EDAC in the protocols, or budgeting plenty of bandwidth for redundancy, as well as having redundant links. Sometimes one may think that it's possible to just ride out a few errors. One may discover later that with other data traveling the same link, a redesign is called for; it's best to anticipate these problems.
As one can see we, as engineers, need to think through the unobvious aspects of a specification, often to better determine the true requirements. Have you ever encountered a case where in order to have a safe design, one must exceed a specification from a customer by a very large margin to have a safe design?