In complex system-on-chip (SoC) designs with heterogeneous voltage domains, the shift from custom analog IP to automated digital implementation is enabling designers to save several months while they don’t have to worry about schedule slips caused by manual analog customizations.
The manual design process for analog IP—which hasn’t changed much since the inception of ICs during the 1960s—is often a bottleneck in the chip design stage. Any change in the original IP introduces a potential for errors and additional verification work. Moreover, the integration of analog IP onto a chip design is a time-consuming process. Especially, when analog circuits are susceptible to the on-chip surroundings.
That’s why the highly manual analog design process, which typically takes several months, is now giving way to automated generation of code for analog IP blocks. The automatically-generated analog IP saves integration time and effort.
Here, it’s worth noting that automatically-generated analog IP isn’t synonymous with off-the-shelf analog IP. Instead, analog IP generators bring the previously generated custom-design blocks into the design flow and employ specialized tools to tailor a suitable IP within hours.
After installing IP generation software, engineers can input their parameters into the existing digital tools and automatically generate analog IP quickly and efficiently.
Automated generators use digital design and verification tools to deliver optimized and process-portable analog IPs in hours. Source: Movellus
Movellus, which automatically generates analog IPs using digital implementation tools and standard cells, offers a portfolio of PLLs, DLLs, and LDOs for use in semiconductor and system designs at advanced process nodes. The analog IP supplier received a second round of funding from Intel Capital in December 2018.
Mythic, an AI chipmaker, has integrated PLL from Movellus in its chip design. “When we needed to push a metal stack change, Movellus was able to provide a correct IP in a matter of hours,” said Mythic CTO David Fick.
Agile Analog also offers customization and automation of code generation for its analog IP blocks. The Cambridge, England-based company founded by former Arm and CSR executives, has over eight IP blocks available, including an ADC, DAC, LDO, and temperature sensor.
Agile Analog offers an initial delivery package (IDP) and a final IP delivery package (FDP). IDP is available very early and provides designers with time to integrate analog IP into their chip development process; moreover, it enables design engineers to provide feedback to be implemented in the FDP.
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