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Basics of Bench Silicon Validation – PCB Passives

Introduction

Validating an IC design comes with unique challenges and considerations. This article provides a refresher on the overlooked or forgotten fundamentals behind commonly used practices, techniques, and rituals to validate the design specifications in the lab. Though the article refers to bench testing, most of the concepts apply to both automated test equipment (ATE) or a bench test platform.

Typical Bench Setup

Figure 1

Typical Bench Setup Diagram

Typical Bench Setup Diagram

A typical bench setup consists of:

  • PCB board which houses the device under test (DUT).
  • Bench-top instruments to force/sense V/I and provide digital patterns for generation/capture, as well as a scope for visual inspection for timing tests.
  • Software to control the DUT board/instruments and generate reports in an automated setup (optional). Automation ensures the consistency of setup configurations, provides reliable measurements, and reduces human error in post processing/data-logging.

A typical test PCB contains connectors to route external sources in/out, active and passive components for signal conditioning/switching, and programmable devices to support automation. One or the other passive components (R, L, and C) is present in every PCB, and most commonly used active devices are operational amplifiers (op-amps), transistors, and diodes. In this article, we’ll focus on the active role played by these PCB passive components and the impact on DUT measurements.

A capacitor is primarily a charge-storing device that stores electrostatic potential energy in the electric field created between two conductive materials separated by a dielectric. The capacitance of any capacitor depends on its geometrical construction and the type of dielectric material. For example, a parallel plate capacitor’s capacitance (C) is given by C = εA /d , where ε is the permittivity of the dielectric material, A is the cross-sectional area, and d is the separation distance between the two terminals.

For a capacitor charged to a given potential difference (V), a material with higher permittivity will hold more charge in a smaller form factor. Capacitors are categorized into different categories, based on the type of dielectrics, voltage ratings, current handling capacity, form factors, etc.

Table 1

Types of commercially available capacitors based on dielectric materials.

Types of commercially available capacitors based on dielectric materials.

The most commonly used surface mount (SMD) capacitors in a typical lab setup are ceramics and electrolytic types:

  • Ceramic capacitors are most commonly used in lab evaluation boards due to their low ESR and linear distribution of voltage across the terminal. Below tables show the different classes and standard nomenclature of SMD ceramic capacitors.

Table 2

Primary differences between two commonly used SMD Ceramic Capacitors.

Primary differences between two commonly used SMD Ceramic Capacitors.

Table 3

EIA-RS-198 naming convention followed by Class 1 SMD ceramics from 25oC to 85oC.

EIA-RS-198 naming convention followed by Class 1 SMD ceramics from 25o C to 85o C.

Table 4

EIA-RS-198 naming convention followed by Class 2 SMD ceramics.

EIA-RS-198 naming convention followed by Class 2 SMD ceramics.

Based on Table 3, the C0G capacitor is the best in its class with zero temperature drift and a tolerance of +/-30ppm/K. Similarly, a X7R capacitor can be decoded to have a tolerance of +/-15% over an operating range of -55o C to 125o C. A Class 1 capacitor may look like an obvious choice for most applications, but usage in small-space applications could be limited by its volumetric inefficiency compared to a Class 2 X7R.

Though ceramic capacitors have the advantage of temperature stability and a high dielectric constant, they do have poor DC bias characteristics (the rate of change in capacitance with regard to change in applied voltage). A Class 2 capacitor can experience as much as 50% capacitance derating over a DC bias range of 0-6V, so it’s a good idea to use a 2-3 times higher capacitor value if it is a system requirement to maintain a minimum capacitance for a DC bias voltage range.

  • Electrolytic capacitors use oxide as their preferred dielectric while the cathode is composed of electrolyte. For example, aluminum electrolytic capacitors use aluminum oxide as their dielectric and manganese oxide as a cathode. Tantalum capacitors have more permittivity than the aluminum ones and, hence, offer more capacitance in a similar footprint than the aluminum ones. In general, surface-mount electrolytic capacitors have more ESR and ESL than ceramic, but their capacitances can go to 1000μF or more. It is common practice to use polarized tantalum capacitors right at the PCB main power connector, where it acts as a circuit breaker in case the user misconnects the positive and negative supplies.

Most PCB designers deal with the capacitor in the below applications:

  • Bypass capacitors are placed on DUT supply pins and reject any sudden changes in voltage across their terminals, thus filtering the AC ripple on the supply rail and providing a clean DC voltage. In a typical PCB design, one would use bigger electrolytic capacitors (300μF) at the board power junction and use low ESR/low-footprint multiple ceramic X7R/X5R (Class 2) in parallel physically close to the DUT supply pins . It is universal practice to place a high-value (1-10μF) and low-value (1-100nF) capacitor to bypass the low frequency and decouple the most common radio frequencies, respectively. For high-frequency noise decoupling on the source line, one needs to consider ceramic capacitors as RLC circuits (parasitic ESL, ESR with negligible leakage resistance) and calculate the capacitor value to set the ESR-ESL-C to the resonant frequency specific to the hardware requirement. At this resonant frequency, the inductive and capacitive reactance cancel each other, thus providing the lowest impedance (ESR) path to the ground.
  • The bypass capacitors should be placed as close as possible to the DUT supply pins to minimize the trace parasitic inductance between the capacitor and DUT pins. Though COG capacitors seem to be the obvious choice for this application due to their excellent temperature drift and superior DC bias characteristics, it is difficult to find high capacitor values (1-100μF) in the smallest 0204 package In such a situation. As a result, one is forced to choose X7R for a smaller form factor in order to place it in a tight space close to the DUT. Figure 2 illustrates the change in a 24-bit delta-sigma ADC) PSRR measurement due to absence or physical placement of the bypass capacitor away from the DUT (2 inches) and closer to the DUT (0.2 inches).

Figure 2

FFT of MAX11254 ADC output conversion codes shows the AC noise magnitude from the supply.

FFT of MAX11254 ADC output conversion codes shows the AC noise magnitude from the supply.

  • Charge reservoir capacitors are extensively used in signal-conditioning products like successive approximation register (SAR) ADCs. The external charge reservoir capacitor should be at least 20 times the internal sampling capacitor (CS ), which helps in charge transfer during the acquisition phase. This strategy limits the drop of the sampled voltage to 5% and helps to settle the ADC within 0.5LSB during the acquisition time (tacq ). A typical value of an ADC internal sampling capacitor is ≅ approximately 50pF, which makes a 1nF C0G SMD capacitor an ideal candidate as an external filter capacitor. Based on the resolution (N) of ADC, the minimum number of time constants required to settle to 0.5LSB is (N+1) *ln(2). This constrains the filter resistance to R= ( tacq /(0.693*[N +1]*20*Cs ), assuming that the settling is limited by the external filter. The combined RC filter sets the bandwidth of the input AC signal and the driving op-amp.
  • Compensation capacitors are used to stabilize high-performance op-amps while, for instance, driving capacitive loads much bigger than the specified maximum load. Compensation capacitors are used for in-loop compensation techniques, which help to counteract the effect of the additional pole introduced by the output load capacitor and the output impedance of the op-amp. This helps in achieving -20dB/decade slope at the crossover frequency. When an op-amp tries to drive a CL >> CLmax , the output will oscillate due to instability caused by a shift of the output pole caused by CL pole as shown in Figure 3.

Figure 3

Click here for larger image 
MAX44246 with CL= 5.5nF (> CLmax = 310pF) with 50kHz square-wave input.”  border=”0″ /></p>
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MAX44246 with CL = 5.5nF (> CLmax = 310pF) with 50kHz square-wave input.

One way to analyze the op-amp’s stability problem is by a method known as “noise gain compensation.” Noise gain, N(s), is the inverse transfer function of the feedback factor β (s ). Adding a pole in the overall transfer function of the op-amp is essentially equivalent to adding a zero in the noise gain transfer function. Every op-amp can be modeled as:

where A (s ) = open loop gain, A(s )β (s ) = loop gain, and ACL (s ) = closed-loop transfer function.

The point of the intersection of A(s) with 1/β (s ) = N (s ), gives the crossover frequency of the op-amp. For the circuit to be stable, the total phase at the crossover frequency should be much less than -180o (phase margin), or the slope at the crossover frequency should be less than -40dB/decade.

Figure 4

Click here for larger image 
Bode plot of op-amp in unity gain configuration driving a capacitive load.

Bode plot of op-amp in unity gain configuration driving a capacitive load.

When an op-amp tries to drive a CL > CLmax , then the load capacitance introduces a pole below the crossover frequency and, hence, has a slope of -40dB/decade at the crossover frequency as shown in Figure 4.

In order to compensate the op-amp to drive higher capacitive loads, there are two commonly used methods: out-of-loop compensation and in-loop compensation. The out-of-loop compensation uses an isolation resistor to stabilize the op-amp and is covered in detail in a section on resistors. The major drawback of out-of-loop compensation is that it requires a large series resistance, which causes significant voltage drop when the op-amp is driving large load currents. On the other hand, the in-loop compensation (Figure 5) uses a very small isolation series resistance (Riso ) and a compensation capacitor (CF ).

Figure 5

MAX44246 op-amp circuit configured for in-loop compensation.

MAX44246 op-amp circuit configured for in-loop compensation.

Figure 6

Click here for larger image 
Bode plot of op-amp configured for in-loop-compensation.

Bode plot of op-amp configured for in-loop-compensation.

The compensation capacitor introduces a pole (fPCF) which nullifies the zero (fZCL) of the load capacitor. Similarly, the pole from the load capacitor (fPCL) is nullified by the zero of the compensation capacitor (fZCF ):

If we equate to nullify the pole-zero pair, we get:

Using a known value of Ro for MAX44246, CF and Riso are calculated to be 1nF and 5Ω, respectively, such that they drive at least 40nF of load capacitance (7x CL ) at a gain of ≅2x.

Figure 7

Click here for larger image 
Op-amp configured for in-loop compensation, driving a 5.5nF load.

Op-amp configured for in-loop compensation, driving a 5.5nF load.

While the in-loop compensation does not require a large isolation resistor and, therefore, has advantages when large load currents are required, it does reduce the closed-loop bandwidth, sometimes significantly.

  • Coupling capacitors are placed between the differential input terminals of devices to remove the common mode noise and to improve CMRR. Since the noise has a dependence on temperature, typically a C0G capacitor is used to keep the capacitance (and its ESR) constant over temperature. The experiment below shows the effect of the coupling capacitor (1nF C0G) on the 24-bit delta-sigma ADC INL measurements at 1ksps data rate.
Figure 8

Effect of coupling capacitor on MAX11254 ADC INL measurements

Effect of coupling capacitor on MAX11254 ADC INL measurements

  • Parasitic capacitance is unwanted capacitance created on PCB boards, and every PCB designer should watch out for it. Two closely spaced signal traces can create a lateral parasitic capacitance within the same layer, or an unwanted capacitor can be created by overlapping trace/power planes on different layers. Guard rings are used to avoid noise injection between two high-speed signals on the same layer, while a ground plane sandwiched between two signal layers provides vertical isolation.

Inductors are passive devices that store energy in a magnetic field. The inductance of an inductor is defined as the change in flux with respect to the change in electric current. As we know from basic laws of electromagnetism, any current-carrying inductor produces a voltage across its terminal which is given by:

Where L is the inductance (H) and is represented by the formula below:

Where, leff = effective mean length of magnetic field in the core, µ0 = permeability of free space (4µ*10-7 Vs/1 Am), µr = relative permeability of the core, and Aeff = effective area of core/magnetic flux.

Inductors play a vital role in many electronic applications. Below we look at some important applications, where various properties on inductors are used to select a specific inductor for a specific application.

  • Energy storing/transferring in DC-DC switching regulators: The performance metrics of DC-DC regulators critically depends on inductors. As per the datasheet, the recommended inductor range for the a 1A buck regulator is from 1µH-1.5µH. As the DC resistance (DCR) of an inductor increases with its inductance (Table 5), one may be misled to infer that using a 1.5µH inductor will be less power efficient than 1µH primarily due to high DCR losses.
Table 5

Key specs to consider while choosing an inductor.

Key specs to consider while choosing an inductor.

Figure 9

Efficiency versus inductance for MAX38643 buck regulator with different inductors.

Efficiency versus inductance for MAX38643 buck regulator with different inductors.

Figure 9 shows power efficiency (η) measurements for the 1A buck regulator with Vin= 5V, Vout=3.3V for two different inductors (1µH and 1.5µH). It shows that the efficiency for light load current range is higher with 1.5µH rather than 1µH, and the 1µH inductor provides better efficiency than 1.5µH above 500mA because of the decreased DCR.

In order to understand what other factors, in addition to the inductor DCR, affect the regulator losses or efficiency, we model all the lossy components in a synchronous DC-DC buck regulator as shown in Figure 10. The components on the left side of the dotted line are internal to the IC, whereas external components are shown on the right side.

Figure 10

Click here for larger image 
Generic model of DC-DC buck switching regulator with lossy components.

Generic model of DC-DC buck switching regulator with lossy components.

Where RDSon_HS = RDS-on of the high-side power FET, and RDSon_LS = RDS-on of the low-side power FET, ton = time period where high-side power FET conducts, toff = time period where low-side power FET conducts, L = inductor value, tidle = time between skip pulses where neither switch is on.

For the 1A buck regulator, the peak-to-peak inductor ripple current (ΔiL_p2p ) is the same for all inductor values, as it uses fixed peak current in DCM mode. Because the peak-to-peak inductor ripple current is fixed, a higher inductor value transfers more energy into the output capacitor and the idle time increases between skip pulses as shown in Figure 11.

Figure 11

Click here for larger image 
Timing diagram of inductor current ripple in DCM mode.

Timing diagram of inductor current ripple in DCM mode.

Hence, a higher inductor value forces the converter to switch less often than a smaller inductor value. Thus, the overall loss of energy over a given time is lower with a large inductor value than with a small inductor value, which explains why 1.5µH provides better efficiency than 1µH at lower load currents.

The above example explains the role of the inductor in deciding efficiency of DC-DC switching regulators. Similarly, the choice of inductor for a given DC-DC converter architecture affects other key parameters like peak-peak ripple voltage, load/line transients, efficiency, and stability.

  • A tuning element in electronic oscillators/filters: Inductors in conjunction with capacitors are used in active/passive filters and oscillators to resonate at a frequency given by 1/(2π√LC). This tuned circuit is exploited in oscillators to synthesize signals at integer multiples of the tuned frequency and in filter circuits to allow/reject AC signals at the tuned frequency to pass into the system. Since the real inductors and capacitors have resistance with them, the effectiveness of tuned tank circuits is given by the Q-factor (1/R*√(L/C)), where R is the equivalent series resistance. For an ideal circuit, where R is almost zero, Q is very high (limR →0 Q = &#8734). This appears as overshoot with ringing in various circuits.
  • Resistors are the most basic electrical component and almost every electrical/electronic device has resistive property (parasitic).

    • Resistor divider is a basic voltage scaling scheme. One of the common uses of the voltage divider is to set the gain of both the inverting and non-inverting signal path in op-amps and programmable gain amplifiers (Figure 12). In a precision application, the resistor divider (R2/R1=R4/R3) mismatch between the two differential pins should be very small for the output to be balanced and have maximum common mode noise rejection. R5C2 and R6C3 used as a front-end filter/charge reservoir to the ADC inputs and R5/R6=C3/C2 should be maintained as close as possible in order to have the same filter/timing characteristic for differential signals.
    Figure 12

    Front-end differential signal path for an ADC.

    Front-end differential signal path for an ADC.

    • Isolation resistor for op-amp compensation: As discussed in the section on capacitors, isolation resistors are a simple, cheap, and space-efficient way to compensate op-amps driving CL > CLmax (Figure 3). Adding an out-of-loop isolation resistor (Figure 13) introduces a zero in the closed-loop transfer function, which tries to nullify the effect of the pole added by the load capacitor. The datasheet of a low-noise, precision op-amp provides a plot of stability versus output load capacitance, the bode plot, and other details. Based on these details, a value of 55Ω was chosen as the isolation resistor (Riso ).
    Figure 13

    Op-amp configured for out-of-loop compensation.

    Op-amp configured for out-of-loop compensation.

    Figure 14

    Click here for larger image 
Op-amp configured for out-of-loop compensation with a 55Ω isolation resistor.

    Op-amp configured for out-of-loop compensation with a 55Ω isolation resistor.

    The major advantage of out-of-loop compensation is that it requires a resistor only versus RC to stabilize the op-amp and simplify the op-amp application circuit. Since the value of the isolation resistor is relatively huge when compared to in-loop-compensation, the voltage drop across the isolation resistor limits the op-amp output voltage range.

    • Thermal noise generated by resistors is given as V n 1 =√(4kTRf )), where k is the Boltzmann constant (k=1.38*10-23 J/K) and T is the absolute temperature in K. For front-end amplifiers and filters, the thermal noise increases with the increase in resistance and the bandwidth (Δf). For example, a 1Ω resistor generates 0.128nV/√Hz of thermal noise density at 25o C. The effect of thermal noise generated by resistors can be understood by looking at the input-referred noise table from the datasheet of the 24-bit delta-sigma ADC used in our experiments (MAX11254). The primary source of noise in the ADC is the thermal noise of the internal resistor of the programmable gain amplifier (PGA). Figure 15 shows that the output-referred noise of this IC increases with the increase in gain setting (as resistance increases) and also increases with the sampling data rate of the ADC, which is equivalent to increasing the bandwidth (Δf).
    Figure 15

    Max11254 PGA output referred noise.

    Max11254 PGA output referred noise.

    The above trade-off applies to the usage of a resistor in the PCB design as well. One needs to be careful of introducing unintentional thermal noise due to usage of a resistor in sensitive signal paths.

    • Proper termination resistance is needed to minimize reflection of a high-speed signal and to maximize power transfer from source to destination. The reflection coefficient (Γ) of a transmission line of characteristic impedance Z0 is given by Γ=Vi /Vr =(RL Z 0 )/(RL +Z0 ), where RL is the termination resistance. So, in order to minimize reflection, on has match termination resistance RL (=Z0 ) to the source impedance, including the cable length. Any commercial coaxial cable with an inner diameter d and outer diameter D can be modeled as lumped capacitance, inductance, and characteristic impedance as follows:

    Although the above equation gives a generic formula for measuring characteristic impedance of coaxial cables, the most common commercially available coaxial cables have either 50Ω or 75Ω impedance and should be terminated with appropriate termination resistors to retain signal integrity.

    SUMMARY

    Though R, L, and C are the basic electronic components, a good understanding of their material, construction, and behavior is needed in order to make the right choice in accordance to the application requirements. It’s not a one-size-fits-all kind of situation. So, the next time you’re working on a PCB design, pay attention to your passive bill of materials (BOM). After all, the passive components aren’t really passive.

    About the authors

    Sarvesh Miyan is a Director of Product Engineering at Maxim Integrated. He manages a bench silicon validation team for a wide variety of products ranging from complex devices like precision ADCs, DACs, and power accumulators to simple linear regulators, references, LED drivers, real-time clocks (RTCs), and more. He has an MSEE with major academic focus on mixed-signal analog design from San Jose State University and has worked as a IC design research associate, test engineer, and application engineer in the past.

    Shyam Sundar Shankar is a Product Engineer at Maxim Integrated and has a strong understanding/experience of validating various complex mixed signal semiconductor ICs like precision Data Converters, DC-DC converter, Real Time Clocks and Supervisory products. Prior to joining Maxim, Shyam has worked as an Applications Engineering at Intersil focusing on DC-DC converters. Shyam Sundar Shankar holds a Master of Science degree in Electrical and Computer Engineering from University of Florida. He also holds a Bachelor of Technology degree in Electrical Engineering from Indian Institute of Technology (IIT) Patna, India.

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