Basics of chip/package codesign in a large flipchip application (Part 2 of 2)

(You can read Part 1 of this article by clicking here)

BGA ball assignment
Assignment of the BGA balls for this kind of signal must consider both the requirements of the package and of the application PC board. Routability and signal quality must be maintained in both. In all cases, the plus and minus signals of each differential pair should be kept together. Separating these pairs from each other by reference voltages balls will give some isolation between the signals, and provide good continuity for the signal return paths and the reference voltages, Figure 6 .

Figure 6: SERDES Ball Usage
(Click to Enlarge Image)

Signal routing
Signal-line dimensions of width and space must be chosen to achieve the specified differential impedance and tolerance while keeping within the limits of manufacturing. The dimensions must also allow sufficient routability in the substrate. Substrate manufacturer's recommendations are very useful here, because they can consider their manufacturing tolerances and effects such as non-rectangular line cross-sections. In the example part, line width was 27 microns, and the space was 47 microns. Figure 7 demonstrates “good” signal routing for these differential signals.

Figure 7: SERDES signal paths
(Click to Enlarge Image)

Lengths have been controlled to align the arrival times of the plus and minus signals of each pair. Suitable space must be maintained between pairs to control coupling. In this case, a space of 100 microns (3x the distance from the trace to the ground planes) guaranteed that the coupling between pairs was less than 4%. The electrical performance of an interconnect like this should be checked by simulation. Figure 8 shows typical results of such simulation, indicating good performance

Figure 81: Cross-section of build-up substrate
(Click to Enlarge Image)

DDR Example
A high-speed parallel bus, such as a double data rate (DDR) memory interface, requires a different approach because the speeds are lower but the number of signals involved is much larger.
The design of such a bus requires a lot of interaction between the functions of I/O placement, redistribution layer (RDL) design, bump placement and assignment, substrate routing, and ball assignment.

Following an initial placement of the peripheral I/O cells and initial assignment of the BGA balls, the design problem becomes one of placing and assigning the bumps such that both the redistribution (from I/O cell to bump) and the substrate routing (from bump to ball) can be achieved with acceptable characteristics. Important constraints on the RDL design include line width and space, dc resistance of the paths (some will be carrying relatively large currents), and current density (to control electromigration). In the substrate routing, the design is constrained by the available line width and space, the need to escape from the high-density bump area, the desired characteristic impedance, delay (length) differences between signals, and controlling crosstalk between signals.

Often many of the RDL paths will have constraints on minimum width and maximum length, to limit electromigration and dc resistance. This can cause the available routing space to fill up very quickly, and I/O-to-bump assignments will be determined by the available routing space in the RDL. It may be necessary to update several times with the I/O designer, modifying the I/O placement and bump assignment as the design progresses. Figure 9 shows a small portion of an example RDL layer design.

Figure 9: Example of redistribution routing
(Click to Enlarge Image)

In a fast bus, it is necessary to provide enough power and ground balls placed among the signal balls to control simultaneous switching noise. Unfortunately, the situation is complicated and it is difficult to state any general rule on the number of balls required. As always, the performance of the desired configuration should be checked by simulation.

Layer usage can follow the bump locations, as it did in the SERDES. In our example design, ground bumps connect directly to a ground plane on the surface layer of the substrate, signals are carried on the next two layers, and power is on the lower layer of the substrate. The signals are thus in a “dual stripline” configuration, with the ground plane above and the power plane below. This is not as good electrically as the stripline of the SERDES signals, but the speeds here are lower and the requirements are less stringent. Because the signal layers are adjacent, care must be taken to control coupling between the layers. This can be done by assigning signals to balls in a way that minimizes traces running parallel on the two layers. Figure 10 shows a portion of the signal routing for the DDR.signals.

Figure 10: Example of DDR routing
(Click to Enlarge Image)


A great deal of cooperative work was required to package this complex, high-speed IC in the desired BGA. Good cooperation and communication between IC design, substrate design, RDL design, assembly process, substrate manufacturing, and electrical modeling and simulation made this part successful.

About the author
Rich Evans , Senior Staff Engineer at STMicroelectronics, earned his BS in Physics and MS in Measurement and Control from Carnegie-Mellon University, Pittsburgh Pennsylvania, USA. He worked at Digital Equipment Corporation from 1979 to 1994, where he was responsible for many aspects of signal integrity and electrical analysis, ranging from IC packages to printed circuit boards to networks.

Rich is currently in the Corporate Package Development group at STMicroelectronics in Carrollton, Texas, where he supplies package electrical models, guides package design to assure good performance, and designs custom Ball Grid Array packages. His current work focuses on power distribution, switching noise, and high-speed serial links.

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