In Parts 1, 2, and 3 we took a closer look at calculating â€śacâ€ť gain and how to desensitize the circuit to temperature and transistor parameter variations. In part 4 we consider the effects of a coupling capacitor and how to achieve higher gain.

In Figure 6, in Part 3, we added an input coupling capacitor (C1). The main purpose of the capacitor is to â€śdecoupleâ€ť the ac signal source from the DC bias network. However, the capacitor introduces a â€śpoleâ€ť (frequency dependent X_{C} ). X_{C} interacts with the source impedance, the biasing network and with a finite beta, the base input resistance (generally dominated by beta*R_{E} ).

Because of the capacitor, the gain of the amplifier at DC must be zero. Depending upon the R and C values selected and the particular non-ideal characteristics of the transistor, the resulting AC response could look like that below in Figure 7. Note that effects of beta, R_{O} , R_{L} and the biasing network have been taken into account to yield a mid-band gain of 10 (20dB).

**Figure 7**

The parasitic junction capacitances and other factors determine the transistorsâ€™ high-frequency performance. C_{cb} can be particularly significant due to gain multiplication (i.e., the Miller Effect). Depending upon the transistor characteristics and other layout-induced capacitive and inductive effects, a decrease in gain is to be expected at â€śhighâ€ť frequencies.

**Achieving higher gain**

As suggested earlier, designs with resistive loads greatly limit the possible gain with a practical power supply voltage. You will recall that this is due primarily to the I_{C} *R_{L} voltage drop. What if we could produce a relatively high impedance load without the I_{C} *R_{L} voltage drop? Well, we can by using additional â€śactiveâ€ť components (transistors) to replace the passive resistive load. This is not to suggest that adding additional transistors in this way is necessarily practical for a discrete design. Rather, I simply wish to show the possibilities.

**Figure 8**

Transistors T2 and T3 form a â€ścurrent mirror.â€ť The current flowing in T2 is nominally V1/R (actually [V1-V_{beT2} ]/R). If we assume that T2 and T3 are well matched and at the same temperature, the emitter current of both transistors will be the same. Note that their base-emitters are in parallel, so their V_{BE} are the same. Actually, however, their collector currents will not be exactly the same. This is due to the finite output impedance of T3. Note that T2s collector-base voltage is zero, while V_{CB} of T3 can change. However, to a first approximation, I_{T3} = V1/R.

This example is intended to demonstrate the concept of a transistor current source (e.g., high Ro) replacing a passive resistive load. Note that the R_{1} , R_{2} biasing suggested here is still too simplistic for a practical â€śdiscreteâ€ť circuit design. Again, the reason is that the DC operating point would be highly dependent upon the supply voltage, temperature, and transistor matching. If we were designing an integrated circuit, we would have the luxury of almost unlimited devices to compensate for the above limitations.

In Part 5 we will see how to minimize output loading to maintain high gain.

The price to be paid for adding the current mirror bias circuitry is an increased area occupation in IC layout and the need of an accurate matching of the transistors , the emitter area of both transistors has to be accurately selected.

You are correct. Â Current mirrors are “easily” implemented in IC form, but more difficult in discrete designs for the matching reasons you mention. Â Nevertheless, it can be successful. Thank you for your comment.

I have no idea on ever making these mirrors in BJT. I will prefer a process that supports CMOS and BJT so that I can do most of the designs in CMOS. BJT is not that hugely popular owing to its poor integration density and high static power dissipation.

In Figure 6, in Part 3, we added an input coupling capacitor (C1).What figure 6?

Â There's no figure 6 in part 3.

I apologize for this oversight.Â Figures 6, and the paragraph describing it, were accidently omitted.

Figure 6 is the same as Figure 5 with the addition of C1 connecting an input signal source to the base of the transistor.

The missing text should read:

In Figure 6, we see the input coupling capacitor (C1).Â The main purpose of the capacitor is to “decouple” the ac signal source from the DC bias network.Â However, the capacitor introduces a “pole” (frequency dependent X

_{C}).Â X_{C}interacts with the source impedance, the biasing network and with a finite beta, the base input resistance (generally dominated by beta*R_{E}).Thank you for catching this.

@HowardS6, you're welcome. The current mirror circuit for discrete is however useful provided a really accurate matching of the discrete transistors and a effective soldering to set the delta VBE being the same for both of the transistors.

In a non-ic version, if making a current mirror, use a multi bi-polar package. The process of making the part is typically using adjacent die since they are pulled off the wafer one-by-one. Drawback is that one part may grab part from different wafers if one is not lucky. Otherwise, if the die pull is in a zig-zag fashion off the wafer, all die pulled should be within proximity of each other.

That's correct, the matching of different parts coming from different wafer might be not good, with the exception of a very stable diffusion process, having no drifts.

@HowardS6: Each time a capacitor is inserted in a high impedance point, the capacitor introduces a pole which interferes with the dominant pole, so it has to be compensated, many times the Miller effect helps to avoid this issue