Bipolar Transistor Circuit Design & Analysis, Part 5

In previous parts of this series we reviewed the basic transistor parameters that determine ac voltage gain and practical considerations limiting high gain. The role of a coupling capacitor was introduced. In this section we see how to minimize output loading to maintain high gain along with more practical DC biasing.

Minimizing the Output Load Effect
It is important to note that the voltage gain at T1 could be heavily influenced by the output load. In Figure 9, yet another transistor (T4) is added to act as an output buffer to maintain higher impedance at the collector of the gain stage (T1). While this “emitter follower” has a voltage gain of one, it has significant current gain (β).

Figure 9

Practical biasing

Figure 10

In Figures 10 and 11 a practical way to bias T1 is suggested. R1 replaces the previous voltage divider. Note that R1 is connected to the collector of T1 (as highlighted in red) and not the power supply. This introduces additional negative feedback to further stabilize the operating point. This technique tends to “automatically” adjust T1s operating point to T3s output current. However, as a result of the feedback, gain is reduced. Still, much higher gains are possible than with a passive load.

Tailoring the feedback
The proper use of feedback, involving passive R and C components is very powerful, not only for circuit stabilization, but for creating desired frequency characteristics.

The example in Figure 11 involves placing a capacitor in parallel with RE (in this case, R2+R3). This allows stabilizing the DC operating point without limiting the mid-band gain. However, a disadvantage of this technique is that it can dramatically decrease the input impedance (β*RE ) as frequency increases.

The red dotted lines suggest another variation. By bypassing only a portion of RE , you can optimize the ac and DC characteristics to suit a particular application. Figure 12 suggests a possible result.

Figure 11

Figure 12

Demonstrated in this series has been an easy way of visualizing the terminal impedances of a bipolar transistor. With this understanding, one can design simple, yet reliable, voltage or current gain stages to satisfy a variety of interface needs. Also suggested were “advanced” techniques to optimize performance for a particular application.

In the next and last part of this series we will summarize the most important points.

4 comments on “Bipolar Transistor Circuit Design & Analysis, Part 5

  1. etnapowers
    March 26, 2014

    The transistor T4 is a common collector stage, this configuration is really useful because it has gain=1 and moreover an high input impedance and a low output impedance , so it is a good decoupler circuit. Many common operational amplifiers have an additional gain stage to increase the gain of the common emitter stage and the decoupling is done once again by a common collector stage.

  2. etnapowers
    March 31, 2014

    The common collector stage solution is more effective when considering a MOS transistor, because of its quite infinite gate impedance.

    I'd like to see a blog series on this, it will be for sure as interesting as this series on BJT transistors.


  3. Davidled
    April 2, 2014

    Firstly, emitter follower is very useful for Zener diode regular because of buffering caused by impedance matching and current amplify.  Secondly, this circuit could be used for signal amplifier IC as gain is maximized at a certain frequency range.

  4. etnapowers
    April 2, 2014

    DaeJ, that's correct, moreover the emitter follower is one of the stages of gain of a integrated operational amplifier, it ensures a tunable gain constant in a quite wide range of frequency and  the signal components within the bandwidth are amplified accordingly.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.