As CMOS semiconductor density advances, ICs are getting faster while the number of high-speed nets multiplies. Interconnects at the board and system level have become the limiting factor to increased system performance and EMI compliance. Every engineer working on high-performance systems has an EMI or signal-integrity horror story, rooted in limited engineering insight. The challenges of designing high-performance systems will not diminish. Waiting to debug a product until after prototype fabrication may result in problems later on. Proper signal-integrity analysis and EMI engineering-up front-will reduce product costs and will rarely impose product-introduction delays.
A transmission-line view of pc-board interconnects lets the engineer analyze various interconnect topologies between the individual system modules, at different levels of physical implementation detail. To develop high-speed products, design teams should leverage maximum performance, not just from the processors and logic but also from the board interconnects. Engineers should have the basis to make trade-offs among timing, signal-integrity, EMI, thermal and other issues to optimize design performance before committing a board-level design to detailed place-and-route. Post-layout verification at the end of the design cycle is the wrong time to evaluate system interconnects.
A number of analog EDA tools on the market materially assist the design process. It is possible to place critical components on a pc-board outline to explore timing or thermal issues, connect device pins to interconnects and connectors, experiment with clocks, control net topology and analyze board area, with an eye to optimal signal integrity.
Signal-integrity analysis products are available from major suppliers of EDA software. Most of the products use I/O Buffer Information Specification (IBIS) models to express the transistor drivers and receivers in their signal-integrity analysis suites. IBIS is a standard for electronic behavioral specifications of integrated circuit input/output analog characteristics. Spice transistor-level models are often withheld by semiconductor vendors, since the model parameters can reveal intellectual-property details of a proprietary semiconductor technology. Consequently, IBIS models are increasingly the only transistor-model information available.
One of the newest Star-Hspice releases, 98.4, allows the mixing of transistor-level semiconductor models with the behaviorally defined IBIS I/O models. This is a significant advance; previously, only limited behavioral modeling capability existed in Spice. For other flavors of Spice, Intusoft provides a free IBIS-to-Spice converter, which converts IBIS 1.1 and 2.1 (partially) data-sheet information into Spice models.
IBIS should be thought of as a behavioral modeling specification suitable for transmission-line simulation of Digital Systems and applicable to most digital components. It encompasses an extensive syntax and data structure for expressing the action of I/O sections of semiconductor devices. The spec provides the input/output device characteristics through the use of device V/I and voltage vs. time data without disclosing any circuit or process information.
An example of a “right by design” approach to a difficult crosstalk problem, IBIS-based simulation can be used to predict the effect of crosstalk in a semiconductor package, so-called simultaneous switching output (SSO) noise. IBIS has the key parameters required to model an SSO event. These are mainly the package inductance, other associated parasitics and the number and type of buffers switching. IBIS specifies the package R, L and C in matrix format. The use of a coupled matrix for the inductance accounts for the “loop” inductance, such as the mutuals between the pins.
Specifying the mutual inductance is necessary to account for SSO event simulation. Simulating SSO, like simulating many signal-integrity phenomena, depends on the accuracy of the model, the skill of the engineer and the simulator used.
IBIS models can be created from a transistor-level Spice description by using the executable “s2ibis” (Spice to IBIS) software, which is freely available through the IBIS Open Forum. For a semiconductor manufacturer or engineer to verify that a device model conforms to the IBIS specification, the model file description should be run through the Golden Parser software developed by the IBIS Open Forum. The Golden Parser, ibischk3, is a free, publicly available executable code that parses the model file. The parser is available in object-code format for many platforms and can be downloaded via anonymous ftp from the vhdl.org BBS (22.214.171.124). It resides under the /pub/ibis/ibischk3 directory. The Golden Parser source code is also available from the EIA IBIS committee for a fee.
In addition to checking syntax, the parser creates data structures from model data that simulators can use. All model files must pass the parser before a model can be released to vhdl.org. The release of new models is handled by the IBIS librarian.