Breakthrough analog-to-digital conversion technology delivers speed, resolution at half the power of current solutions

Xignal Technologies AG today announced a breakthrough in analog-to-digital converter (ADC) technology. Utilizing proprietary architectural advances in continuous time delta sigma (CTΔΣ) conversion, Xignal’s innovative architecture enables the design of high resolution (12-bits and above) ADCs that convert at up to several hundred megahertz effective sampling rates on a power budget less than half that of existing pipeline solutions. Moreover, the breakthrough is accomplished in mainstream 130 nm CMOS technology that is available from a wide variety of foundries. This facilitates a high degree of functional integration including an on-chip, low-jitter, precision clock that eliminates the need for external timing circuits.

Xignal’s CTΔΣ technology will produce the world’s lowest power ADCs, by far. The technology enables alias-free Nyquist sampling, which means that anti-aliasing filters are not needed, so system cost is reduced. ADCs based on the technology will have easy-to-drive differential inputs, eliminating a costly input differential amplifier and further reducing external component count. The integrated precision sampling clock also cuts design complexity. Crucially, the technology scales with the CMOS process roadmap, making it future-proof.

Xignal has already demonstrated the CTΔΣ technology in the laboratory and is preparing first commercial products to be released in the coming months.

Industry’s lowest power ADC technology – bar none
Power consumption is reduced because continuous time design methods are inherently lower power than discrete time. The latter use sampled discrete time circuits that have to slew continuously on each sample clock edge to track and hold the input signal. This requires very high speed, power-hungry circuits. Moving to a continuous time sampling system, where the input signal is integrated over the full sample period, eliminates the sample and hold amplifier (SHA) to give a significant reduction in power consumption. This is best demonstrated by calculating the conversion power efficiency figure of merit (FOM) recognised by the IEEE as an objective comparison method to assess individual merits of ADC architectures. Xignal’s ADC returns better than 0. 5 pJ/conv (picojoules/conversion) compared to greater than 1 pJ/conv for best-in-class pipeline designs.

The CTΔΣ architecture does not generate the aliased errors in the frequency-domain found with pipelined architectures. Neither external anti-aliasing filters, nor power-hungry over-sampling techniques (used to reduce external filter complexity) are required to eliminate aliased errors in the sampled base-band. This significantly reduces both system cost and power consumption, and enables CTΔΣ operation up to the Nyquist limit, without compromising performance.

The input stage equivalent circuit of Xignal’s CTΔΣ ADC is a simple resistive load rather than the complex capacitive impedance used in contemporary switched-capacitor systems. This not only eliminates the need for discrete differential drivers but also means that signal path components, such as low-noise amplifiers and programmable gain amplifiers can be integrated on-chip to achieve further reductions in system size and cost.

In high dynamic range systems, errors in the sample clock can lead to decibels (dBs) of lost dynamic performance (SNR). Xignal solves this problem by exploiting its LC-PLL expertise. Products using CTΔΣ technology will include a low jitter, on-chip LC-PLL, which may either be supplied by a low cost crystal or a medium-performance external clock, removing any further clock design effort.

A further important advantage of Xignal’s breakthrough is scalability with shrinking process geometry. Today Xignal is designing CTΔΣ ADCs on 0.13 μm CMOS and has demonstrated 12-bit resolution sampling at 40 MSPS on a 1.2 V supply. In future, process scaling will yield further performance (speed and power) improvements and cost reductions over time – something that pipeline ADCs are already struggling to do.

“ADCs based on CTΔΣ technology will appeal to designers of low power systems who demand high dynamic range at high sample rates and are challenged by space. Next generation portable ultrasound is an excellent example where CTΔΣ will be of high value.” stated Mark Holdaway, Xignal’s Marketing Director. “Also, by exploiting a mixed signal implementation, Xignal gains a versatile and flexible technology platform able to target a broad range of ADC resolutions and sample rates.”

More information about the technology is available at

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